IP Library Granted Patent US 10,431,577
Granted Patent B2
US 10,431,577 · App. 15/892,625 · Granted Oct 1, 2019

Methods of forming circuit-protection devices

Inventors: Michael A. Smith (Boise, ID); Kenneth W. Marr (Boise, ID)
Assignee: Micron Technology, Inc.
H01L27/0266G11C16/22H01L21/28035H01L21/28158H01L21/3212H01L21/823456H01L21/823462H01L21/823475H01L27/11526H01L27/11573H01L29/0649G11C16/0483G11C16/10G11C16/14G11C16/26H01L21/31116H01L21/32137
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,431,577
App. No.
15/892,625
Granted
Oct 1, 2019
Kind
B2
Abstract

Methods of forming a circuit-protection device include forming a dielectric having a first thickness and a second thickness greater than the first thickness over a semiconductor, forming a conductor over the dielectric, and patterning the conductor to retain a portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness, wherein the retained portion of the conductor defines a control gate of a field-effect transistor of the circuit-protection device.

Claims (20)

1. A method of forming a circuit-protection device, comprising:

forming a dielectric having a first thickness and having a second thickness, greater than the first thickness, over a semiconductor;

forming the dielectric further having a third thickness greater than the second thickness, over the semiconductor;

forming a conductor over the dielectric;

patterning the conductor to retain a first portion of the conductor over a portion of the dielectric having the second thickness, and to retain substantially no portion of the conductor over a portion of the dielectric having the first thickness; and

patterning the conductor to further retain a second portion of the conductor over a portion of the dielectric having the third thickness;

wherein the retained first portion of the conductor defines a control gate of a first field-effect transistor of the circuit-protection device; and

wherein the retained second portion of the conductor defines a control gate of a second field-effect transistor of the circuit-protection device connected in series with the first field-effect transistor.

2. A method of forming a circuit-protection device, comprising:

forming a first dielectric over a first portion of a semiconductor;

forming a second dielectric over the first portion of the semiconductor, over a second portion of the semiconductor, and over a third portion of the semiconductor;

removing a portion of the second dielectric over the third portion of the semiconductor;

forming a third dielectric over the first portion of the semiconductor, over the second portion of the semiconductor, and over the third portion of the semiconductor;

forming a conductor over the third dielectric; and

patterning the conductor to retain a first portion of the conductor over the first portion of the semiconductor and a second portion of the conductor over the second portion of the semiconductor.

3. The method of claim 2 , further comprising removing a portion of the first dielectric prior to forming the second dielectric.

4. The method of claim 2 , wherein forming the second dielectric comprises forming the second dielectric to comprise the first dielectric, and wherein forming the third dielectric comprises forming the third dielectric to comprise the second dielectric.

5. The method of claim 2 , further comprising removing a portion of the third dielectric over the third portion of the semiconductor.

6. The method of claim 5 , wherein removing the portion of the third dielectric over the third portion of the semiconductor comprises removing an entire portion of the third dielectric over the third portion of the semiconductor.

7. The method of claim 2 , further comprising patterning the conductor to retain substantially no portion of the conductor over the third portion of the semiconductor.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2018
From: SMITH, MICHAEL W.; MARR, KENNETH W.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 044879/0448 →
Continuity (2)
Provisional Application 62611874 · Dec 29, 2017
Related Publication 20190206856A1 · Jul 4, 2019