Generating and using invertible, shortened Bose-Chaudhuri-Hocquenghem codewords

1. A computer-implemented method for using invertible, shortened codewords, comprising:

receiving a request to store user data bits in a set of memory devices;

expanding the user data bits and an inversion bit to bit locations of a codeword template, wherein the expanding forms expanded inversion and user data bits that collectively include additional bits to represent the user data bits and the inversion bit, wherein the inversion bit indicates whether the user data bits are inverted, wherein the codeword template maps a first set of bit positions corresponding to the user data bits and the inversion bit to a second set of bit positions corresponding to the expanded inversion and user data bits;

generating parity bits for the expanded inversion and user data bits to form a shortened codeword, wherein the shortened codeword comprises the expanded inversion and user data bits, and the parity bits;

compressing the shortened codeword to form a compressed shortened codeword, wherein the compressed shortened codeword has fewer bits than the shortened codeword; and

storing the compressed shortened codeword in the set of memory devices.

2. The computer-implemented method of claim 1 , wherein the shortened codeword comprises one or more bits that a decoder determines are “zeroes” without reading corresponding portions of the shortened codeword.

3. The computer-implemented method of claim 1 , further comprising:

detecting an event associated with the compressed shortened codeword; and

in response to detecting the event, inverting the compressed shortened codeword such that the compressed shortened codeword is stored in the set of memory devices in an inverted state.

4. The computer-implemented method of claim 3 , wherein the event is passage of a predefined time since storing the compressed shortened codeword in the set of memory devices.

5. The computer-implemented method of claim 1 , further comprising:

receiving a request for the user data bits from a host system;

expanding, in response to receiving the request for the user data bits, the compressed shortened codeword according to the codeword template to form the shortened codeword;

decoding the shortened codeword to generate a user data bit output and the inversion bit; and

outputting, to the host system, the user data bit output or an inverted version of the user data bit output based on a value of the inversion bit.

6. The computer-implemented method of claim 1 , further comprising:

determining a length for an inversion and user data bit portion of a vector of bits, wherein the inversion and user data bit portion of the vector comprises “ones” for all bit positions;

increasing the length of the inversion and user data bit portion of the vector until a number of “ones” in the inversion and user data bit portion and the parity bits generated for the inversion and user data bit portion of the vector is greater than the selected length of the inversion and user data bit portion of the vector;

rotating the vector to place the vector in systematic form such that the inversion and user data bit portion of the vector is placed in the least significant bits side of the vector;

selecting, and starting with the most significant bits of the vector, a first set of bit positions that have a value of one to denote the inversion bit;

selecting, and starting with the least significant bits of the vector, a second set of bit positions to denote the parity bits; and

selecting a third set of bit positions that have not been selected for the inversion bit or the parity bits to denote the user data bits,

wherein the selections of the first set of bit positions, the second set of bit positions, and the third set of bit positions collectively represent the codeword template.

7. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to:

receive a request to store user data bits to the memory device expand the user data bits and an inversion bit to bit locations of a codeword template, wherein the expanding forms expanded inversion and user data bits that collectively include additional bits to represent the user data bits and the inversion bit, wherein the inversion bit indicates whether the user data bits are inverted, wherein the codeword template maps a first set of bit positions corresponding to the user data bits and the inversion bit to a second set of bit positions corresponding to the expanded inversion and user data bits,

generate parity bits for the expanded inversion and user data bits to form a shortened codeword, wherein the shortened codeword comprises the expanded inversion and user data bits, and the parity bits,

compress the shortened codeword to form a compressed shortened codeword, wherein the compressed shortened codeword has fewer bits than the shortened codeword, and

store the compressed shortened codeword in the set of memory devices.

8. The system of claim 7 , wherein the shortened codeword comprises one or more bits that a decoder determines are “zeroes” without reading corresponding portions of the shortened codeword.

9. The system of claim 7 , wherein the processing device is further to:

detect an event associated with the compressed shortened codeword; and

in response to detecting the event, invert the compressed shortened codeword such that the compressed shortened codeword is stored in the set of memory devices in an inverted state.

10. The system of claim 9 , wherein the event is passage of a predefined time since storing the compressed shortened codeword in the set of memory devices.

11. The system of claim 7 , wherein the processing device is further to:

receive a request for the user data bits from a host system;

expand, in response to receiving the request for the user data bits, the compressed shortened codeword according to the codeword template to form the shortened codeword;

decode the shortened codeword to generate a user data bit output and the inversion bit; and

output the user data bit output or an inverted version of the user data bit output based on a value of the inversion bit.

12. The system of claim 7 , wherein the processing device is further to:

determine a length for an inversion and user data bit portion of a vector of bits, wherein the inversion and user data bit portion of the vector comprises “ones” for all bit positions;

increase the length of the inversion and user data bit portion of the vector until a number of “ones” in the inversion and user data bit portion and the parity bits generated for the inversion and user data bit portion of the vector is greater than the selected length of the inversion and user data bit portion of the vector;

rotate the vector to place the vector in systematic form such that the inversion and user data bit portion of the vector is placed in the least significant bits side of the vector;

select, starting with the most significant bits of the vector, a first set of bit positions that have a value of one to denote the inversion bit;

select, starting with the least significant bits of the vector, a second set of bit positions to denote the parity bits; and

select a third set of bit position that have not been selected for the inversion bit or the parity bits to denote the user data bits,

wherein the selections of the first set of bit positions, the second set of bit positions, and the third set of bit positions collectively represent the codeword template.

13. A non-transitory machine-readable storage medium, which stores instructions that, when executed by a processor of a controller, cause the controller to:

expand user data bits and an inversion bit to bit locations of a codeword template, wherein the expanding forms expanded inversion and user data bits that collectively include additional bits to represent the user data bits and the inversion bit, wherein the inversion bit indicates whether the user data bits are inverted, wherein the codeword template maps a first set of bit positions corresponding to the user data bits and the inversion bit to a second set of bit positions corresponding to the expanded inversion and user data bits;

generate parity bits for the expanded inversion and user data bits to form a shortened codeword, wherein the shortened codeword comprises the expanded inversion and user data bits, and the parity bits;

compress the shortened codeword to form a compressed shortened codeword, wherein the compressed shortened codeword has fewer bits than the shortened codeword; and

store the compressed shortened codeword in a set of memory devices.

14. The non-transitory machine-readable storage medium of claim 13 , wherein the shortened codeword comprises one or more bits that a decoder determines are “zeroes” without reading corresponding portions of the shortened codeword.

15. The non-transitory machine-readable storage medium of claim 13 , wherein the instructions further cause to the memory controller to:

detect an event associated with the compressed shortened codeword; and

in response to detecting the event, invert the compressed shortened codeword such that the compressed shortened codeword is stored in the set of memory devices in an inverted state.

16. The non-transitory machine-readable storage medium of claim 15 , wherein the event is the passage of a predefined time since storing the compressed shortened codeword in the set of memory devices.

17. The non-transitory machine-readable storage medium of claim 13 , wherein the instructions further cause to the memory controller to:

receive a request for the user data bits from a host system;

expand, in response to receiving the request for the user data bits, the compressed shortened codeword according to the codeword template to form the shortened codeword;

decode the shortened codeword to generate a user data bit output and the inversion bit; and

output, to the host system, the user data bit output or an inverted version of the user data bit output based on a value of the inversion bit.

18. The non-transitory machine-readable storage medium of claim 13 , wherein the instructions further cause to the memory controller to:

determine a length for an inversion and user data bit portion of a vector of bits, wherein the inversion and user data bit portion of the vector comprises “ones” for all bit positions;

increase the length of the inversion and user data bit portion of the vector until a number of “ones” in the inversion and user data bit portion and the parity bits generated for the inversion and user data bit portion of the vector is greater than the selected length of the inversion and user data bit portion of the vector;

rotate the vector to place the vector in systematic form such that the inversion and user data bit portion of the vector is placed in the least significant bits side of the vector;

select, starting with the most significant bits of the vector, a first set of bit positions that have a value of one to denote the inversion bit;

select, starting with the least significant bits of the vector, a second set of bit positions to denote the parity bits; and

select a third set of bit position that have not been selected for the inversion bit or the parity bits to denote the user data bits, wherein the selections of the first set of bit positions, the second set of bit positions, and the third set of bit positions collectively represent the codeword template.