Stacked memory devices, systems, and methods
Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.
1. A method, comprising:
receiving at an interface device a memory request from a processor, the memory request received over a first bus between the processor and the interface device having a first width and operable at a first speed in an interface device;
in response to the received memory request, the interface device performing a cache tag look-up routine in multiple memory devices operably coupled to the interface device, and at least one storage device coupled to the interface device;
wherein the multiple memory devices are coupled to the interface device through a second bus having a second width wider than the first width of the first bus, and
wherein the at least one storage device comprises a flash memory module coupled to a solid-state drive control circuit, wherein the solid-state drive control circuit is coupled to the interface device through a third bus, wherein the third bus is narrower than the second width of the second bus;
the cache tag look-up routine determining that only a first portion of the selected information is in one or more of the multiple memory devices memory devices;
accessing the multiple memory devices to retrieve the first portion of the selected information and storing the retrieved first portion of the selected information as first information in the interface device;
determining that a second portion of the selected information is in the at least one storage device; and
accessing at least one storage device to retrieve the second portion of the selected information and storing the retrieved second portion of the selected information as second information in the interface device.
2. The method of claim 1 , wherein the multiple memory devices are stacked relative to one another and are interconnected through vertical conductive channels extending through the multiple stacked memory devices.
3. The method of claim 2 , wherein the second bus comprises the vertical conductive channels extending through the multiple memory devices in the stack.
4. The method of claim 1 , further comprising transmitting the first information and the second information to the processor that transmitted the memory request.
5. The method of claim 2 , wherein the each of the stacked multiple memory devices is a dynamic random access memory (DRAM) device.
6. The method of claim 5 , wherein the stack of dynamic random access memory (DRAM) devices is further stacked with the interface device, and the stack of DRAM devices is further coupled to the interface device through the vertical conductive channels.
7. The method of claim 1 , wherein the at least one storage device comprises at least one solid-state disk (SSD).
8. The method of claim 1 , wherein the interface device further performs the cache tag lookup routine in a DRAM DIMM coupled to the interface device through a fourth bus, the DRAM DIMM separate from the multiple memory devices coupled to the interface device through the second bus.
9. The method of claim 2 , wherein the stacked memory devices are operated as cache memory.
10. A system, comprising:
an interface device configured to couple to a processor through a first high-speed bus, the first bus having a first width;
a stack of multiple DRAM memory devices stacked with the interface device and coupled to one another and to the interface device through a second bus having a second width wider than the first width of the first bus; and
at least one storage device coupled to the interface device through a third bus;
wherein the interface device is configured to,
receive a memory request for selected information,
perform a cache tag look-up routine in the multiple stacked DRAM memory devices and the at least one storage device,
select a device from the storage device and the multiple stacked DRAM memory devices, based on the selected device having the shortest latency for retrieving at least a first portion of the selected information,
retrieve and store the selected information, and
transmit the information to the processor.
11. The system of claim 10 , wherein retrieving and storing the selected information comprises:
determining that the selected device contains only a first portion of the selected information;
retrieving the first portion of the information from the selected device; and
retrieving at least a second portion of the selected information from the storage device.
12. The system of claim 10 , wherein the interface device is further operable to store at least one of cache tag values and logical block address (LBA) tables in the stack of multiple DRAM memory devices.
13. The system of claim 10 , wherein the second bus comprises multiple conductive channels extending vertically from the interface device to each of the stacked DRAM memory devices.