Stacked memory devices, systems, and methods
View Patent ↗Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.
1. A method, comprising:
receiving, in an interface device coupled to multiple memory devices and at least one storage device, a memory request for selected information;
performing a cache tag look-up routine in the multiple memory devices and the at least one storage device, the cache tag lookup-up routine performed by the interface device;
determining that only a first portion of the selected information is in a first of the memory devices;
accessing the first memory device to retrieve the first portion of the selected information and storing the retrieved first portion of the selected information as first information in the interface device;
determining that a second portion of the selected information is in a second of the multiple memory devices or in the at least one storage device; and
accessing the second memory device or the at least one storage device to retrieve the second portion of the selected information and storing the retrieved second portion of the selected information as second information in the interface device.
2. The method of claim 1 , further comprising transmitting the first information and the second information to a device that transmitted the memory request.
3. The method of claim 2 , wherein the device that transmitted the memory request is a processor.
4. The method of claim 3 , wherein the processor does not perform a disk input/output routine to retrieve the first information and the second information.
5. The method of claim 1 , wherein the multiple memory devices are arranged in a stack.
6. The method of claim 5 , wherein the stack includes multiple dynamic random access memory (DRAM) devices coupled to the interface device through a plurality of channels.
7. The method of claim 1 , wherein the memory devices include multiple dynamic random access memory (DRAM) devices.
8. The method of claim 1 , wherein the at least one storage device comprises non-volatile memory.
9. The method of claim 1 , wherein the at least one storage device comprises at least one solid-state disk (SSD).
10. A method, comprising:
sending a memory request for selected information from a processor to an interface device coupled to a stack including two or more memory devices and to at least one storage device; and
receiving the information in the processor from the interface device after the interface device has,
performed a cache tag look-up routine to select a device from a storage device and the stack based upon the device having the shortest latency for retrieving at least a first portion of the selected information,
retrieved and stored the selected information, and
transmitted the information to the processor.
11. The method of claim 10 , wherein the interface device has further:
determined that the selected device contains only a first portion of the selected information; and
retrieved at least, a second portion of the selected information from a storage device.
12. The method of claim 10 , wherein the stack including two or more memory devices comprises one or more of a dynamic random-access memory (DRAM) device and a flash memory device.
13. The method of claim 10 , further comprising storing cache tag values or logical block address (LBA) tables in the stack.
14. The method of claim 10 , wherein the processor does not perform a disk input/output routine to retrieve the selected information.
15. A system comprising:
a processor;
multiple memory devices;
at least one storage device; and
an interface device coupled to the processor, the multiple memory devices, and the at least one storage device, the interface device configured to,
receive a memory request for selected information;
in response to receipt of the memory request, perform a cache tag look-up routine in the multiple memory devices and the at least one storage device;
determine that only a first portion of the selected information is in a first of the memory devices;
access the first memory device to retrieve the first portion of the selected information and store the retrieved first portion of the selected information as first information in the interface device;
determine that a second portion of the selected information is in a second of the multiple memory devices or in the at least one storage device; and
access the second memory device or the at least one storage device to retrieve the second portion of the selected information and storing the retrieved second portion of the selected information as second information in the interface device.
16. The system of claim 15 , wherein the interface device is further configured to transmit the first information and the second information to a device that transmitted the memory request.
17. The system of claim 15 , wherein the multiple memory devices are arranged in a stack.
18. The system of claim 17 , wherein the stack includes multiple dynamic random access memory (DRAM) devices coupled to the interface device through a plurality of channels.
19. The system of claim 15 , wherein the multiple memory devices include multiple dynamic random access memory (DRAM) devices.
20. The system of claim 15 , wherein the at least one storage device comprises at least one solid-state disk (SSD).