Patent Assignment
Reel/Frame 050695/0825
Release of Security Interest
Recorded: 2019-10-09
Pages: 35
Assignor
MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Executed: 2019-07-31
Assignee
MICRON TECHNOLOGY, INC.
8000 S FEDERAL WAY, BOISE, IDAHO, 83707
Covered Properties
(321)
Method for Packaging Circuits
Stacked Microfeature Devices and Associated Methods
Method and Apparatus Providing Pixel Array Having Automatic Light Control Pixels and Image Capture Pixels
Memory Arrays
Program and Read Trim Setting
Block or Page Lock Features in Serial Interface Memory
High Aspect Ratio Openings
Semiconductor with Through-Substrate Interconnect
Methods of Forming Diodes
Application:
15/354,572 →
Publication:
US US20170069732A1
Stacked Memory Devices, Systems, and Methods
Memory Bank Signal Coupling Buffer and Method
Semiconductor Substrates with Unitary Vias and via Terminals, and Associated Systems and Methods
Access Line Management in a Memory Device
Conditional Operation in an Internal Processor of a Memory Device
Methods and Apparatuses for Reducing Power Consumption in a Pattern Recognition Processor
Ohmic Contacts for Semiconductor Structures
Line Termination Methods
Light Emitting Devices with Built-in Chromaticity Conversion and Methods of Manufacturing
Application:
15/385,690 →
Publication:
US US20170104126A1
Solid State Lighting Devices with Reduced Crystal Lattice Dislocations and Associated Methods of Manufacturing
Sense Operation Flags in a Memory Device
Programmable Device, Heirarchical Parallel Machines, and Methods for Providing State Information
Solid State Lighting Devices with Accessible Electrodes and Methods of Manufacturing
Apparatus Including Gettering Agents in Memory Charge Storage Structures
Memory Devices Having Source Lines Directly Coupled to Body Regions and Methods
Solid State Optoelectronic Device with Plated Support Substrate
External Gettering Method and Device
Methods of Forming Conductive Elements of Semiconductor Devices and of Forming Memory Cells
Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells
Conductive Structures, Systems and Devices Including Conductive Structures and Related Methods
Semiconductor Constructions
Methods of Forming and Using Fuses
Memory Cells Including a Metal Chalcogenide Material and Related Methods
Memory Management for a Hierarchical Memory System
Boolean Logic in a State Machine Lattice
Methods and Systems for Power Management in a Pattern Recognition Processing System
Stair Step Formation Using at Least Two Masks
Clamp Elements for Phase Change Memory Arrays
Apparatuses and Methods for Providing Data from a Buffer
Sequence Power Control
Multi-Junction Solid State Transducer Devices for Direct Ac Power and Associated Systems and Methods
Arrays of Memory Cells and Methods of Forming an Array of Memory Cells
Method of Assembly Semiconductor Device with Through-Package Interconnect
Autorecovery After Manufacturing/System Integration
Apparatuses Having a Ferroelectric Field-Effect Transistor Memory Array and Related Method
Integrated Circuitry and Methods of Forming Transistors
Vertical Ferroelectric Field Effect Transistor Constructions, Constructions Comprising A Pair Of Vertical Ferroelectric Field Effect Transistors, Vertical Strings Of Ferroelectric Field Effect Transistors, And Vertical Strings Of Laterally Opposing Pairs Of Vertical Ferroelectric Field Effect Transistors
Comparison Operations in Memory
Methods and Apparatuses Having Strings of Memory Cells and Select Gates with Double Gates
Cross-Point Memory and Methods for Fabrication of Same
Semiconductor Devices and Packages and Methods of Forming Semiconductor Device Packages
Semiconductor Device Assemblies Including Intermetallic Compound Interconnect Structures
Semiconductor Device Packages with Improved Thermal Management and Related Methods
Apparatuses and Methods of Reading Memory Cells
Apparatuses and Methods for Setting a Signal in Variable Resistance Memory
Soft Post Package Repair of Memory Devices
Magnetic Tunnel Junctions, Methods Used While Forming Magnetic Tunnel Junctions, and Methods of Forming Magnetic Tunnel Junctions
Comparison Operations in Memory
Methods of Forming Resistive Memory Elements
Apparatuses and Methods for Storing a Data Value in Multiple Columns
Transistors and Memory Arrays
Patent:
9,842,840 →
Application:
15/347,623 →
Transistors and Methods of Forming Transistors
Bonding Pads with Thermal Pathways
Estimating an Error Rate Associated with Memory
Secure Subsystem
Offset Compensation for Ferroelectric Memory Cell Sensing
Apparatuses and Methods for Asymmetric Bi-Directional Signaling Incorporating Multi-Level Encoding
Graph Traversal Using Automata Processor
Application:
62/410,686 →
Stacked Semiconductor Die Assemblies with High Efficiency Thermal Paths and Molded Underfill
System and Method for Write Data Bus Control in a Stacked Memory Device
Memory Devices Which Include Memory Arrays
Boolean Satisfiability
Application:
62/410,722 →
Apparatuses and Methods for Memory Alignment
Memory Arrays Comprising Ferroelectric Capacitors
Patent:
9,847,337 →
Application:
15/391,699 →
Voltage Generation Circuit
Memory Arrays
Patent:
9,773,728 →
Application:
15/391,025 →
Memory Arrays
Methods of Forming Patterns, and Apparatuses Comprising Finfets
Patent:
9,853,027 →
Application:
15/391,405 →
Apparatuses and Methods for Single Level Cell Caching
Memory Arrays
Timing Based Arbiter Systems and Circuits for Zq Calibration
Patent:
9,767,921 →
Application:
15/396,259 →
Wireless Devices and Systems Including Examples of Mixing Input Data with Coefficient Data
Conductive Structures, Wordlines and Transistors
Apparatuses and Methods for Dynamic Voltage and Frequency Switching for Dynamic Random Access Memory
Two-Step Data-Line Precharge Scheme
Apparatuses and Methods for Calibrating Adjustable Impedances of a Semiconductor Device
Application:
62/432,494 →
Apparatus and Method for a Pvt Independent Rc Delay
Memory Cells and Methods of Forming a Capacitor
Apparatuses and Methods for a Memory Device with Dual Common Data I/O Lines
Patent:
9,805,786 →
Application:
15/400,653 →
Methods of Forming Memory Arrays
Interconnect Structure with Nitrided Barrier
Semiconductor Devices Comprising Nitrogen-Doped Gate Dielectric
Patent:
9,922,885 →
Application:
15/365,126 →
Wireless Devices and Systems Including Examples of Mixing Coefficient Data Specific to a Processing Mode Selection
Patent:
9,942,074 →
Application:
15/365,397 →
Wireless Devices and Systems Including Examples of Cross Correlating Wireless Transmissions
Apparatus and Method of Power Transmission Sensing for Stacked Devices
Apparatuses and Methods for Power Efficient Driver Circuits
Patent:
9,911,469 →
Application:
15/348,578 →
Uniform Electrochemical Plating of Metal Onto Arrays of Pillars Having Different Lateral Densities and Related Technology
Patent:
9,905,527 →
Application:
15/380,877 →
Apparatuses and Methods for High Speed Writing Test Mode for Memories
Floating Body Transistors and Memory Arrays Comprising Floating Body Transistors
Patent:
9,773,788 →
Application:
15/391,656 →
Identifying Asynchronous Power Loss
Patent:
9,921,898 →
Application:
15/390,833 →
Methods of Forming Integrated Circuitry
Patent:
9,666,573 →
Application:
15/335,259 →
Custom Compute Cores in Integrated Circuit Devices
Application:
62/410,732 →
Error Correction to Reduce a Failure in Time Rate
Semiconductor Die Assembly Having Heat Spreader That Extends Through Underlying Interposer and Related Technology
Apparatuses and Methods for Compute Components Formed Over an Array of Memory Cells
Application:
62/419,004 →
Memory Cell, An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor With The Array Comprising Rows Of Access Lines And Columns Of Digit Lines, A 2T-1C Memory Cell, And Methods Of Forming An Array Of Capacitors And Access Transistors There-Above
Patent:
9,842,839 →
Application:
15/404,995 →
Integrated Structures
Patent:
9,773,882 →
Application:
15/405,141 →
Cell Disturb Prevention Using a Leaker Device to Reduce Excess Charge from an Electronic Device
Apparatuses Including Memory Cells and Methods of Operation of Same
Semiconductor Devices with Underfill Control Features, and Associated Systems and Methods
Memory Cells, Integrated Structures and Memory Arrays
Board Edge Connector
Methods Including Establishing a Negative Body Potential in a Memory Cell
Wiring with External Terminal
Methods of Forming an Array Comprising Pairs of Vertically Opposed Capacitors and Arrays Comprising Pairs of Vertically Opposed Capacitors
Magnetic Memory Device with Grid-Shaped Common Source Plate, System, and Method of Fabrication
Multiferroic Magnetic Tunnel Junction Devices
Memory Management
Integrated Memory
Methods Of Forming An Array Of Capacitors, Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And A Transistor, Arrays Of Capacitors, And Arrays Of Memory Cells Individually Comprising A Capacitor And A Transistor
Data Shift Apparatuses and Methods
Patent:
9,761,300 →
Application:
15/358,673 →
Memory Cells, Arrays Of Two Transistor-One Capacitor Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In Fabricating Integrated Circuitry
Application:
62/445,574 →
Directed Sanitization of Memory
Apparatus and Methods for via Connection with Reduced via Currents
Patent:
9,888,574 →
Application:
15/399,664 →
Data Relocation in Hybrid Memory
Memory Operations on Data
Methods of Forming an Array Comprising Pairs of Vertically Opposed Capacitors and Arrays Comprising Pairs of Vertically Opposed Capacitors
Patent:
9,935,114 →
Application:
15/402,679 →
Arrays Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor, Methods Of Forming A Tier Of An Array Of Memory Cells, And Methods Of Forming An Array Of Memory Cells Individually Comprising A Capacitor And An Elevationally-Extending Transistor
Patent:
9,837,420 →
Application:
15/402,463 →
Methods of Forming an Array Comprising Pairs of Vertically Opposed Capacitors and Arrays Comprising Pairs of Vertically Opposed Capacitors
Patent:
9,761,580 →
Application:
15/340,842 →
Memory Protocol
Apparatuses and Methods for Providing Internal Clock Signals of Different Clock Frequencies in a Memory Device
Patent:
9,818,462 →
Application:
15/410,602 →
Semiconductor Device and Error Correction Method
Output Buffer Circuit with Low Sub-Threshold Leakage Current
Semiconductor Device Including Subword Driver Circuit
Device Having Multiple Switching Buffers for Data Paths Controlled Based on Io Configuration Modes
Buffer Operations in Memory
Apparatuses and Methods to Control Body Potential in 3D Non-Volatile Memory Operations
Object Carrier Transport System and Method of Transporting Object Carriers
Cylinder-Shaped Storage Node with Single-Layer Supporting Structure
Application:
14/290,987 →
Publication:
US US20150348963A1
Transistor Structure and Method of Manufacturing the Same
Application:
14/509,151 →
Publication:
US US20160104782A1
Semiconductor Devices Comprising Gate Structure Sidewalls Having Different Angles
Semiconductor Device
Recess Array Device with Reduced Contact Resistance
Application:
14/714,334 →
Publication:
US US20160336413A1
Overhead Traveling Vehicle, Transportation System with the Same, and Method of Operating the Same
Application:
14/986,729 →
Publication:
US US20170194181A1
Electrostatic Chuck and Temperature-Control Method for the Same
Method for Fabricating a Semiconductor Device
Three-Way Valve and Method for Using the Same
Application:
15/013,995 →
Publication:
US US20170219104A1
Methods of Forming Semiconductor Packages Including Molding Semiconductor Chips of the Semiconductor Packages
Semiconductor Structure Having a Patterned Surface Structure and Semiconductor Chips Including Such Structures
Methods of Manufacturing a Multi-Device Package
Methods of Fabricating a Semiconductor Package Structure Including at Least One Redistribution Layer
Wafer Level Package and Fabrication Method Thereof
Package-On-Package Assembly and Method for Manufacturing the Same
Application:
14/735,127 →
Publication:
US US20160365334A1
Semiconductor Devices Including Dummy Chips
Wafer Level Package with Tsv-Less Interposer
Method for Fabricating Semiconductor Package
Memory Device and Fabricating Method Thereof
Memory Device and Fabricating Method Thereof
Fan-Out Wafer Level Packaging and Manufacturing Method Thereof
Patent:
9,576,933 →
Application:
14/989,782 →
Methods of Fabricating a Semiconductor Structure
Method for Manufacturing a Package-on-Package Assembly
Application:
15/003,812 →
Publication:
US US20170213801A1
Package-On-Package Assembly and Method for Manufacturing the Same
Application:
14/931,862 →
Semiconductor Structure Including a Capacitor Structure and Fabricating Method Thereof
Application:
15/003,765 →
Publication:
US US20170213885A1
Wafers Having a Die Region and a Scribe-Line Region Adjacent to the Die Region
Method for Fabricating a Memory Device Having Two Contacts
Fault Isolation System and Method for Detecting Faults in a Circuit
Method for Forming a Patterned Layer
Patent:
9,786,504 →
Application:
15/155,090 →
Development Apparatus and Method for Developing Photoresist Layer on Wafer Using the Same
Application:
15/001,267 →
Publication:
US US20170205712A1
Method of Forming Patterns
Patent:
9,613,820 →
Application:
15/069,936 →
Method of Forming Patterns
Semiconductor Package with Double Side Molding
Patent:
9,613,895 →
Application:
15/060,577 →
Method of Fabricating a Wafer Level Package
Patent:
9,704,790 →
Application:
15/069,911 →
Method of Forming Patterns
Semiconductor Memory Device Having Enlarged Cell Contact Area and Method of Fabricating the Same
Method of Fabricating Semiconductor Memory Device Having Enlarged Cell Contact Area
Method for Fabricating Wafer Level Package
Patent:
9,576,931 →
Application:
15/047,632 →
Semiconductor Package with Sidewall-Protected Rdl Interposer and Fabrication Method Thereof
Patent:
9,570,369 →
Application:
15/068,649 →
Semiconductor Package with Sidewall-Protected Rdl Interposer
Conductive Pads Forming Method
Patent:
9,735,119 →
Application:
15/219,265 →
Semiconductor Package and Fabrication Method Thereof
Patent:
9,761,559 →
Application:
15/135,539 →
Semiconductor Package with Multiple Coplanar Interposers
Patent:
9,721,923 →
Application:
15/098,341 →
Semiconductor Memory Device Having Coplanar Digit Line Contacts and Storage Node Contacts in Memory Array and Method for Fabricating the Same
Semiconductor Package and Fabrication Method Thereof
Patent:
9,786,586 →
Application:
15/242,594 →
Wafer Level Package Utilizing Molded Interposer
Microelectronic Package Utilizing Embedded Bridge Through-Silicon-via Interconnect Component and Related Methods
System and Method for Detecting Fault Events
Application:
15/296,053 →
Publication:
US US20180107202A1
Semiconductor Package and Fabrication Method Thereof
Patent:
9,922,845 →
Application:
15/342,124 →
Multi-Chip Semiconductor Package with via Components and Method for Manufacturing the Same
Patent:
9,607,967 →
Application:
14/977,645 →
Methods of Operating Storage Systems Including Encrypting a Key Salt
Efficient Operations of Components in a Wireless Communications Device
Phase Change Memory Device with Voltage Control Elements
Persistent Content in Nonvolatile Memory
Phase Change Memory in a Dual Inline Memory Module
Memory Cells and Methods of Forming Memory Cells
Methods of Providing Access to I/O Devices
Method of Fabricating Sample Membranes for Transmission Electron Microscopy Analysis
Circuit Structure of Integrated Circuit
Method for Fabricating Semiconductor Device
Method for Forming a Memory Device with C-Shaped Deep Trench Capacitors
Holding Apparatus
Method and System for Detecting Tool Errors to Stop a Process Recipe for a Single Chamber
Fuzzy Control Method for Adjusting a Semiconductor Machine
Method for Prognostic Maintenance in Semiconductor Manufacturing Equipments
Method for Detecting Variance in Semiconductor Processes
Memory Device and Fabrication Method Thereof
Wafer Cassette Transportation Method and System Thereof
Method for Predicting Cycle Time
System for Monitoring Temperature and Slope of a Wafer and a Method Thereof
Observation Method of Wafer Ion Implantation Defect
Gas-Liquid Separation System and Method Thereof
Pressure Control System of Wafer Polishing Apparatus
Method for Automatically Shifting a Base Line
Automatic Recovery and Transport System and Execution Method Therefor
Preparation Method for an Electron Tomography Sample with Embedded Markers and a Method for Reconstructing a Three-Dimensional Image
Mini Clean Room for Preventing Wafer Pollution and Using Method Thereof
Automatic Wafer Storage System and a Method for Controlling the System
Chemical Treatment Apparatus
Method of Cleaning Showerhead
Method for Planning a Semiconductor Manufacturing Process Based on Users' Demands Using a Fuzzy System and a Genetic Algorithm Model
Moving Module of a Wafer Ion-Implanting Machine
Method for Assessing Data Worth for Analyzing Yield Rate
Method for Monitoring Fabrication Parameter
Method for Finding the Correlation Between the Tool Pm and the Product Yield
Method of Adjusting Wafer Processing Sequence
Method for Evaluating Efficacy of Prevention Maintenance for a Tool
Manufacturing Method for Double-Side Capacitor of Stack Dram
Method for Manufacturing Capacitor Lower Electrodes of Semiconductor Memory
Process Using Oxide Supporter for Manufacturing a Capacitor Lower Electrode of a Micro Stacked Dram
Method for Identifying a Wafer Serial Number
Self-Alignment Method for Recess Channel Dynamic Random Access Memory
Method for Detecting Statuses of Components of Semiconductor Equipment and Associated Apparatus
Vertical Pmos Field Effect Transistor and Manufacturing Method Thereof
Vertical Pmos Field Effect Transistor and Manufacturing Method Thereof
Method for Manufacturing Capacitor Lower Electrodes of Semiconductor Memory
Multi-Track Handling and Storage Apparatus and Method Thereof
Low Parasitic Capacitance Bit Line Process for Stack Dram
Device for Preventing Current-Leakage
Method for Detecting Errors of Exposed Positions of a Pre-Layer and a Current Layer by an Integrated Alignment and Overlay Mark
Method for Fabricating Fine Patterns of Semiconductor Device Utilizing Self-Aligned Double Patterning
Electron Microscope Specimen and Method for Preparing the Same
Auxiliary Stage and Method of Utilizing Auxiliary Stage
Manufacturing Method for Fin-Fet Having Floating Body
Memory Layout Structure and Memory Structure
Semiconductor Structure
Developer Spraying Device for Reducing Usage Quantity of Developer
Specification Establishing Method for Controlling Semiconductor Process
Transport System Having Multilayer Tracks and Controlling Method Thereof
Method for Fabricating a Mask
Memory Structure Having a Floating Body and Method for Fabricating the Same
Semiconductor Structure and Fault Location Detecting System
Capacitor Structure and Fabrication Method Thereof
Vertical Transistor for Random-Access Memory and Manufacturing Method Thereof
Exhaust Machine
Method of Planar Imaging on Semiconductor Chips Using Focused Ion Beam
Dram with Dopant Stop Layer and Method of Fabricating the Same
Method and System of Compressing Raw Fabrication Data for Fault Determination
Fault Detection Method of Semiconductor Manufacturing Processes and System Architecture Thereof
Bidirectional Wafer Carrying Pod and Wafer Transfer System
Nand Type Flash Memory for Increasing Data Read/Write Reliability
Fabricating Method of Dram Structure
Memory Layout Structure
Fabricating Method of Insulator
Patent:
8,298,892 →
Application:
13/241,295 →
Semiconductor Structure Having Lateral Through Silicon Via
Method for Adjusting Trench Depth of Substrate
Spin Transfer Torque Random Access Memory
Overhead Hoist Transport System
Door Detection System
Method for Operating an Automatic Handling System Applied to Many Wafer Processing Apparatuses
Overhead Rail Guided Transport System and Implementation Method Thereof
Wafer Stocker
Method of Forming Isolation Area and Structure Thereof
Manufacturing Method for High Capacitance Capacitor Structure
High-K Metal Gate Random Access Memory
Manufacturing Method of Random Access Memory
Overhead Buffer Device and Wafer Transport System
Method of Manufacturing Isolation Structure
Wafer and Film Coating Method of Using the Same
Semiconductor Structure
Semiconductor Layout Structure
Memory Cell Having a Recessed Gate and Manufacturing Method Thereof
Method for Measuring Size of Specimen
Patent:
8,716,661 →
Application:
13/831,763 →
Semiconductor Device and Manufacturing Method Therefor
Memory Unit, Memory Unit Array and Method of Manufacturing the Same
Stacked Capacitor Structure and a Fabricating Method for Fabricating the Same
Memory Device and Method for Manufacturing the Same
Overhead Hoist Transport System
Vertical Transistor and Method to Form Vertical Transistor Contact Node
Non-Floating Vertical Transistor Structure
Method for Manufacturing High-Strength Structural Stacked Caacitor
Capacitor, Storage Node of the Capacitor, and Method of Forming the Same
Patent:
9,018,733 →
Application:
14/201,932 →
Manufacturing Method of Capacitor Structure and Semiconductor Device Using the Same
Method for Forming Self-Aligned Isolation Trenches in Semiconductor Substrate and Semiconductor Device
Manufacturing Method of Capacitor Lower Electrode and Semiconductor Storage Device Using the Same
Dynamic Random Access Memory Unit and Fabrication Method Thereof
Sample Stack Structure and Method for Preparing the Same
Method for Increasing Pattern Density
Semiconductor Device and Fabrication Method Therefor
Probe Unit for Test Tools and Method of Manufacturing the Same
Semiconductor Structure
Patent:
9,171,847 →
Application:
14/505,490 →
Semiconductor Structure and Manufacturing Method Thereof
Patent:
9,397,048 →
Application:
14/664,932 →
Semiconductor Device and Manufacturing Method Thereof
Patent:
9,472,664 →
Application:
14/803,100 →
Recess Array Device
Patent:
9,379,197 →
Application:
14/877,889 →
Split Contact Structure and Fabrication Method Thereof
Patent:
9,401,326 →
Application:
14/720,830 →
Multi-Device Package and Manufacturing Method Thereof
Wafer Level Package Having Redistribution Layer and Fabrication Method Thereof
Patent:
9,449,935 →
Application:
14/810,415 →
Silicon Interposer and Fabrication Method Thereof
Patent:
9,455,243 →
Application:
14/720,840 →
Package-On-Package Assembly and Method for Manufacturing the Same
Patent:
9,437,583 →
Application:
15/134,396 →
Wafer Level Package and Fabrication Method Thereof
Package-On-Package Assembly and Method for Manufacturing the Same
Patent:
9,449,953 →
Application:
14/877,949 →
Method for Forming Cell Contact
Patent:
9,419,001 →
Application:
14/996,240 →
Apparatuses and Methods Including Memory and Operation of Same
PCT:
PCT/US2016/058714 ↗
Apparatuses and Methods for Encoding and Decoding of Signal Lines for Multi-Level Communication Architectures
PCT:
PCT/US2016/069425 ↗
Error Code Calculation on Sensing Circuitry
PCT:
PCT/US2017/012240 ↗
Ferroelectric Capacitor, Ferroelectric Field Effect Transisstor, and Method Used in Forming an Electronic Component Compresing Conductive Material and Ferroelectric Material
PCT:
PCT/US2016/063046 ↗
Semiconductor Devices with Duplicated Die Bond Pads and Associated Device Packages and Methods of Manufacture
PCT:
PCT/US2017/012383 ↗
Apparatuses and Methods for Providing a Signal with a Differential Phase Mixer
PCT:
PCT/US2016/060640 ↗
Data Transfer Techniques for Multiple Devices on a Shared Bus
PCT:
PCT/US2016/058898 ↗
Ferroelectric Devices and Methods of Forming Ferroelectric Devices
PCT:
PCT/US2017/012864 ↗
Partially Written Block Treatment
PCT:
PCT/US2017/014535 ↗
Apparatuses and Methods for Concurrently Accessing Multiple Memory Planes of a Memory During a Memory Access Operation
PCT:
PCT/US2016/059484 ↗
Apparatuses and Methods for Concurrently Accessing Multiple Partitions of a Non-Volatile Memory
PCT:
PCT/US2016/068834 ↗
Apparatuses and Methods for Exiting Low Power States in Memory Devices
PCT:
PCT/US2016/066383 ↗
Related Assignments
(8)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 16, 2014
From: KIEHLBAUCH, MARK W.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032911/0808 →
Assignment of Assignor's Interest
Nov 29, 2016
From: KIRBY, KYLE K.; PAREKH, KUNAL R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040450/0391 →
Supplement No. 3 to Patent Security Agreement
Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
Assignment of Assignor's Interest
Aug 10, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP, LLC
Reel/Frame 064551/0025 →
Assignment of Assignor's Interest
Sep 21, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP, LLC
Reel/Frame 064988/0923 →
Confirmatory License
Oct 23, 2023
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 065313/0397 →