METHOD FOR MANUFACTURING A PACKAGE-ON-PACKAGE ASSEMBLY
A method for fabricating a package-on-package assembly is provided. A carrier with a passivation layer on the carrier is provided. A redistribution layer (RDL) is formed on the passivation layer. The RDL comprises at least one dielectric layer and at least one metal layer. The at least one metal layer comprises a plurality of first bump pads and second bump pads exposed from a top surface of the at least one dielectric layer. The first bump pads are disposed within a chip mounting area, while the second pads are disposed within a peripheral area. At least one chip is then mounted on the first bump pads. The at least one chip is electrically connected to the RDL through first bumps on the first bump pads. A die package is then mounted on the second bump pads. The die package is electrically connected to the RDL through second bumps on the second bump pads.
1 . A method for fabricating a package-on-package (PoP) assembly, comprising:
providing a carrier with a first passivation layer on the carrier;
forming a redistribution layer (RDL) on the first passivation layer, wherein the RDL comprises at least one dielectric layer and at least one metal layer, wherein the at least one metal layer comprises first bump pads and second bump pads exposed from a top surface of the at least one dielectric layer, wherein the first bump pads are disposed within a chip mounting area, and the second bump pads are disposed within a peripheral area around the chip mounting area;
mounting at least one first chip on the first bump pads, wherein the at least one first chip is electrically connected to the RDL through first bumps on the first bump pads;
mounting a die package comprising at least one second chip pre-encapsulated in a first molding compound on the second bump pads, wherein the die package is electrically connected to the RDL through second bumps on the second bump pads; and
encapsulating the die package, the at least one chip, and the RDL in a second molding compound and curing the second molding compound at a temperature lower than a glass transition temperature of the first molding compound.
2 . The method for fabricating a PoP assembly according to claim 1 , wherein before mounting the at least one chip on the first bump pads, the method further comprises:
forming a second passivation layer on the at least one dielectric layer;
forming first and second openings in the second passivation layer to expose respective first and second bump pads; and
forming the first bumps on the respective first bump pads.
3 . The method for fabricating a PoP assembly according to claim 1 , wherein after mounting the die package on the second bump pads, the method further comprises:
de-bonding the carrier to thereby expose a major surface of the first passivation layer;
forming solder balls in or on the first passivation layer; and
performing a dicing process to singulate individual package-on-package assemblies.
4 . The method for fabricating a PoP assembly according to claim 1 , wherein providing the first passivation layer comprises providing an organic material.
5 . The method for fabricating a PoP assembly according to claim 4 , wherein providing the organic material comprises providing a polyimide.
6 . The method for fabricating a PoP assembly according to claim 1 , wherein providing the first passivation layer comprises providing an inorganic material.
7 . The method for fabricating a PoP assembly according to claim 1 , wherein providing the inorganic material comprises providing silicon nitride or silicon oxide.
8 . The method for fabricating a PoP assembly according to claim 1 , wherein forming the redistribution layer comprising the at least one metal layer comprises forming the redistribution layer comprising at least one layer of aluminum, copper, tungsten, titanium, or titanium nitride.
9 . The method for fabricating a PoP assembly according to claim 2 , wherein forming the second passivation layer comprises forming polyimide or a solder mask material.
10 . The method for fabricating a PoP assembly according to claim 1 , wherein mounting the die package comprises mounting a die package comprising second chips pre-encapsulated in the first molding compound.
11 . A package-on-package (PoP) assembly, comprising:
a first passivation layer;
a redistribution layer (RDL) on the first passivation layer wherein the RDL comprises at least one dielectric layer and at least one metal layer, wherein the at least one metal layer comprises first bump pads and second bump pads exposed from a top surface of the at least one dielectric layer, wherein the first bump pads are disposed within a chip mounting area, and the second bump pads are disposed within a peripheral area around the chip mounting area;
at least one chip mounted on the first bump pads, wherein the at least one chip is electrically connected to the RDL through first bumps on the first bump pads;
a die package on the second bump pads, wherein the die package is electrically connected to the RDL through second bumps on the second bump pads, and wherein the die package comprises a first molding compound; and
a second molding compound encapsulating the die package and the RDL, the second molding compound having a curing temperature lower than a glass transition temperature of the first molding compound.
12 . The package-on-package (PoP) assembly according to claim 11 , further comprising:
a second passivation layer on the at least one dielectric layer; and
first openings and second openings in the second passivation layer to expose respective first and second bump pads.
13 . The package-on-package (PoP) assembly according to claim 11 , wherein the first molding compound and the second molding compound have different compositions.