Patent Assignment
Reel/Frame 041820/0815
Assignment of Assignor's Interest
Recorded: 2017-02-27
Pages: 12
Assignor
INOTERA MEMORIES, INC.
Executed: 2017-02-22
Assignee
MICRON TECHNOLOGY, INC.
8000 SOUTH FEDERAL WAY, BOISE, IDAHO, 83707
Covered Properties
(169)
Method of Fabricating Sample Membranes for Transmission Electron Microscopy Analysis
Circuit Structure of Integrated Circuit
Holding Apparatus
Method for Fabricating Semiconductor Device
Method and System for Detecting Tool Errors to Stop a Process Recipe for a Single Chamber
Fabrication Method for Memory Device
Gas-Liquid Separation System and Method Thereof
Fuzzy Control Method for Adjusting a Semiconductor Machine
Method for Predicting Cycle Time
Wafer Cassette Transportation Method and System Thereof
Method for Prognostic Maintenance in Semiconductor Manufacturing Equipments
Method for Forming a Memory Device with C-Shaped Deep Trench Capacitors
Observation Method of Wafer Ion Implantation Defect
Mini Clean Room for Preventing Wafer Pollution and Using Method Thereof
System for Monitoring Temperature and Slope of a Wafer and a Method Thereof
Automatic Recovery and Transport System and Execution Method Therefor
Chemical Treatment Apparatus
Automatic Wafer Storage System and a Method for Controlling the System
Memory Device and Fabrication Method Thereof
Moving Module of a Wafer Ion-Implanting Machine
Method for Assessing Data Worth for Analyzing Yield Rate
Pressure Control System of Wafer Polishing Apparatus
Method for Monitoring Fabrication Parameter
Method for Planning a Semiconductor Manufacturing Process Based on Users' Demands Using a Fuzzy System and a Genetic Algorithm Model
Preparation Method for an Electron Tomography Sample with Embedded Markers and a Method for Reconstructing a Three-Dimensional Image
Method of Adjusting Wafer Processing Sequence
Method for Finding the Correlation Between the Tool Pm and the Product Yield
Method for Evaluating Efficacy of Prevention Maintenance for a Tool
Method for Detecting Statuses of Components of Semiconductor Equipment and Associated Apparatus
Manufacturing Method for Double-Side Capacitor of Stack Dram
Method for Manufacturing Capacitor Lower Electrodes of Semiconductor Memory
Method for Manufacturing Capacitor Lower Electrodes of Semiconductor Memory
Process Using Oxide Supporter for Manufacturing a Capacitor Lower Electrode of a Micro Stacked Dram
Low Parasitic Capacitance Bit Line Process for Stack Dram
Method for Fabricating Fine Patterns of Semiconductor Device Utilizing Self-Aligned Double Patterning
Vertical Pmos Field Effect Transistor and Manufacturing Method Thereof
Method for Identifying a Wafer Serial Number
Device for Preventing Current-Leakage
Method for Detecting Errors of Exposed Positions of a Pre-Layer and a Current Layer by an Integrated Alignment and Overlay Mark
Multi-Track Handling and Storage Apparatus and Method Thereof
Self-Alignment Method for Recess Channel Dynamic Random Access Memory
Manufacturing Method for Fin-Fet Having Floating Body
Memory Layout Structure and Memory Structure
Semiconductor Structure
Auxiliary Stage and Method of Utilizing Auxiliary Stage
Electron Microscope Specimen and Method for Preparing the Same
Developer Spraying Device for Reducing Usage Quantity of Developer
Specification Establishing Method for Controlling Semiconductor Process
Transport System Having Multilayer Tracks and Controlling Method Thereof
Method of Cleaning Showerhead
Vertical Transistor for Random-Access Memory and Manufacturing Method Thereof
Method for Fabricating a Mask
Semiconductor Structure and Fault Location Detecting System
Capacitor Structure and Fabrication Method Thereof
Memory Structure Having a Floating Body and Method for Fabricating the Same
Method for Detecting Variance in Semiconductor Processes
Bidirectional Wafer Carrying Pod and Wafer Transfer System
Nand Type Flash Memory for Increasing Data Read/Write Reliability
Method for Automatically Shifting a Base Line
Dram with Dopant Stop Layer and Method of Fabricating the Same
Method and System of Compressing Raw Fabrication Data for Fault Determination
Fault Detection Method of Semiconductor Manufacturing Processes and System Architecture Thereof
Exhaust Machine
Fabricating Method of Insulator
Patent:
8,298,892 →
Application:
13/241,295 →
Method for Adjusting Trench Depth of Substrate
Spin Transfer Torque Random Access Memory
Overhead Hoist Transport System
Fabricating Method of Dram Structure
Door Detection System
Method for Operating an Automatic Handling System Applied to Many Wafer Processing Apparatuses
Semiconductor Structure Having Lateral Through Silicon Via
Memory Layout Structure
Method of Planar Imaging on Semiconductor Chips Using Focused Ion Beam
Stack Position Determination in Memory Devices Configured for Stacked Arrangements
Patent:
8,891,278 →
Application:
13/365,413 →
Method of Forming Isolation Area and Structure Thereof
High-K Metal Gate Random Access Memory
Manufacturing Method of Random Access Memory
Wafer Stocker
Manufacturing Method for High Capacitance Capacitor Structure
Overhead Buffer Device and Wafer Transport System
Method for Measuring Size of Specimen
Patent:
8,716,661 →
Application:
13/831,763 →
Semiconductor Structure
Semiconductor Layout Structure
Method of Manufacturing Isolation Structure
Memory Unit, Memory Unit Array and Method of Manufacturing the Same
Semiconductor Device and Manufacturing Method Therefor
Memory Cell Having a Recessed Gate and Manufacturing Method Thereof
Stacked Capacitor Structure and a Fabricating Method for Fabricating the Same
Overhead Hoist Transport System
Memory Device and Method for Manufacturing the Same
Wafer and Film Coating Method of Using the Same
Capacitor, Storage Node of the Capacitor, and Method of Forming the Same
Patent:
9,018,733 →
Application:
14/201,932 →
Method for Increasing Pattern Density
Method for Manufacturing High-Strength Structural Stacked Caacitor
Object Carrier Transport System and Method of Transporting Object Carriers
Method for Forming Self-Aligned Isolation Trenches in Semiconductor Substrate and Semiconductor Device
Manufacturing Method of Capacitor Lower Electrode and Semiconductor Storage Device Using the Same
Dynamic Random Access Memory Unit and Fabrication Method Thereof
Manufacturing Method of Capacitor Structure and Semiconductor Device Using the Same
Semiconductor Device and Fabrication Method Therefor
Cylinder-Shaped Storage Node with Single-Layer Supporting Structure
Application:
14/290,987 →
Publication:
US 2015/0348963
Vertical Pmos Field Effect Transistor and Manufacturing Method Thereof
Sample Stack Structure and Method for Preparing the Same
Vertical Transistor and Method to Form Vertical Transistor Contact Node
Semiconductor Structure
Patent:
9,171,847 →
Application:
14/505,490 →
Transistor Structure and Method of Manufacturing the Same
Application:
14/509,151 →
Publication:
US 2016/0104782
Semiconductor Structure and Manufacturing Method Thereof
Patent:
9,397,048 →
Application:
14/664,932 →
Probe Unit for Test Tools and Method of Manufacturing the Same
Non-Floating Vertical Transistor Structure
Recess Array Device with Reduced Contact Resistance
Application:
14/714,334 →
Publication:
US 2016/0336413
Split Contact Structure and Fabrication Method Thereof
Patent:
9,401,326 →
Application:
14/720,830 →
Silicon Interposer and Fabrication Method Thereof
Patent:
9,455,243 →
Application:
14/720,840 →
Semiconductor Devices Including Dummy Chips
Methods of Fabricating a Semiconductor Package Structure Including at Least One Redistribution Layer
Methods of Manufacturing a Multi-Device Package
Semiconductor Structure Having a Patterned Surface Structure and Semiconductor Chips Including Such Structures
Package-On-Package Assembly and Method for Manufacturing the Same
Application:
14/735,127 →
Publication:
US 2016/0365334
Semiconductor Devices Comprising Gate Structure Sidewalls Having Different Angles
Wafer Level Package and Fabrication Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Patent:
9,472,664 →
Application:
14/803,100 →
Wafer Level Package Having Redistribution Layer and Fabrication Method Thereof
Patent:
9,449,935 →
Application:
14/810,415 →
Electrostatic Chuck and Temperature-Control Method for the Same
Multi-Device Package and Manufacturing Method Thereof
Method for Manufacturing a Wafer Level Package
Application:
14/835,687 →
Publication:
US 2017/0062240
Memory Device and Fabricating Method Thereof
Recess Array Device
Patent:
9,379,197 →
Application:
14/877,889 →
Package-On-Package Assembly and Method for Manufacturing the Same
Patent:
9,449,953 →
Application:
14/877,949 →
Wafer Level Package with Tsv-Less Interposer
Methods of Forming Semiconductor Packages Including Molding Semiconductor Chips of the Semiconductor Packages
Wafer Level Package and Fabrication Method Thereof
Package-On-Package Assembly and Method for Manufacturing the Same
Application:
14/931,862 →
Methods of Fabricating a Semiconductor Structure
Fault Isolation System and Method for Detecting Faults in a Circuit
Multi-Chip Semiconductor Package with via Components and Method for Manufacturing the Same
Patent:
9,607,967 →
Application:
14/977,645 →
Overhead Traveling Vehicle, Transportation System with the Same, and Method of Operating the Same
Application:
14/986,729 →
Publication:
US 2017/0194181
Fan-Out Wafer Level Packaging and Manufacturing Method Thereof
Patent:
9,576,933 →
Application:
14/989,782 →
Memory Device and Fabricating Method Thereof
Wafers Having a Die Region and a Scribe-Line Region Adjacent to the Die Region
Method for Fabricating a Memory Device Having Two Contacts
Method for Forming Cell Contact
Patent:
9,419,001 →
Application:
14/996,240 →
Semiconductor Device
Development Apparatus and Method for Developing Photoresist Layer on Wafer Using the Same
Application:
15/001,267 →
Publication:
US 2017/0205712
Semiconductor Memory Device Having Enlarged Cell Contact Area and Method of Fabricating the Same
Method for Fabricating a Semiconductor Device
Method for Fabricating Semiconductor Package
Semiconductor Structure Including a Capacitor Structure and Fabricating Method Thereof
Application:
15/003,765 →
Publication:
US 2017/0213885
Method for Manufacturing a Package-on-Package Assembly
Application:
15/003,812 →
Publication:
US 2017/0213801
Method of Forming Patterns
Three-Way Valve and Method for Using the Same
Application:
15/013,995 →
Publication:
US 2017/0219104
Method for Fabricating Wafer Level Package
Patent:
9,576,931 →
Application:
15/047,632 →
Semiconductor Package with Double Side Molding
Patent:
9,613,895 →
Application:
15/060,577 →
Method of Forming Patterns
Semiconductor Package with Sidewall-Protected Rdl Interposer and Fabrication Method Thereof
Patent:
9,570,369 →
Application:
15/068,649 →
Method of Fabricating a Wafer Level Package
Patent:
9,704,790 →
Application:
15/069,911 →
Method of Forming Patterns
Patent:
9,613,820 →
Application:
15/069,936 →
Patterns Forming Method
Semiconductor Package with Multiple Coplanar Interposers
Patent:
9,721,923 →
Application:
15/098,341 →
Package-On-Package Assembly and Method for Manufacturing the Same
Patent:
9,437,583 →
Application:
15/134,396 →
Semiconductor Package and Fabrication Method Thereof
Patent:
9,761,559 →
Application:
15/135,539 →
Semiconductor Memory Device Having Coplanar Digit Line Contacts and Storage Node Contacts in Memory Array and Method for Fabricating the Same
Method for Forming a Patterned Layer
Patent:
9,786,504 →
Application:
15/155,090 →
Conductive Pads Forming Method
Patent:
9,735,119 →
Application:
15/219,265 →
Semiconductor Package and Fabrication Method Thereof
Patent:
9,786,586 →
Application:
15/242,594 →
Method of Fabricating Semiconductor Memory Device Having Enlarged Cell Contact Area
Microelectronic Package Utilizing Embedded Bridge Through-Silicon-via Interconnect Component and Related Methods
Wafer Level Package Utilizing Molded Interposer
System and Method for Detecting Fault Events
Application:
15/296,053 →
Publication:
US 2018/0107202
Semiconductor Package with Sidewall-Protected Rdl Interposer
Semiconductor Package and Fabrication Method Thereof
Patent:
9,922,845 →
Application:
15/342,124 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 14, 2012
From: CHANG, SHENG-JUNG; FENG, HANG-HAO
To: INOTERA MEMORIES, INC.
Reel/Frame 028199/0369 →
Supplement No. 3 to Patent Security Agreement
Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →