IP Library Patent Application 15296053
Patent Application
App. No. 15/296,053

SYSTEM AND METHOD FOR DETECTING FAULT EVENTS

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Patent No.
US None
App. No.
15/296,053
Abstract

A detection method includes: aligning, by a processor, first data with second data according to steps, in which the first data and the second data are associated with equipment for fabricating semiconductor devices; determining, by the processor, a first virtual area according to the first data; determining, by the processor, a second virtual area according to the second data; and displaying, by a display, a result of comparing the first virtual area and the second virtual area, to distinguish whether a fault event exists during the process.

Claims (43)

1 . A detection method, comprising:

aligning, by a processor, first data with second data according to a plurality of steps, wherein the first data and the second data are associated with equipment for fabricating semiconductor devices;

determining, by the processor, a first virtual area according to the first data;

determining, by the processor, a second virtual area according to the second data; and

displaying, by a display, a result of comparing the first virtual area and the second virtual area, to distinguish whether a fault event exists in the equipment.

2 . The detection method of claim 1 , wherein the first data and the second data are gathered at each of the steps, and the operation of aligning the first data with the second data comprises:

aligning the first data with the second data at the steps.

3 . The detection method of claim 1 , wherein the operation of determining the first virtual area comprises:

determining a first upper limit value and a first lower limit value according to the first data; and

generating the first virtual area according to the first upper limit value and the first lower limit value.

4 . The detection method of claim 3 , wherein the first upper limit value is predetermined times as large as a maximum value of the first data, and the first lower limit value is the predetermined times as large as a minimum value of the first data.

5 . The detection method of claim 3 , wherein the operation of determining the second virtual area comprises:

determining a second upper limit value and a second lower limit value according to the second data; and

generating the second virtual area according to the second upper limit value and the second lower limit value.

6 . The detection method of claim 5 , wherein the second upper limit value is predetermined times as large as a maximum value of the second data, and the second lower limit value is the predetermined times as large as a minimum value of the second data.

7 . The detection method of claim 5 , wherein the operation of displaying the result of comparing the first virtual area and the second virtual area comprises:

comparing, by the processor, the first upper limit value and the first lower limit value with the second upper limit value and the second lower limit value; and

displaying, by the display, the result of comparing the first area with the second area with a plurality indicators that are displayed with different color patterns.

8 . The detection method of claim 7 , wherein a first indicator of the indicators is displayed for indicating that there is no fault events, in a condition that the second upper limit value is less than the first upper limit value, and the second lower limit value is greater than the first lower limit value.

9 . The detection method of claim 7 , wherein a second indicator of the indicators is displayed for indicating that the fault event exists in the equipment, in a condition that the second upper limit value is between the first upper limit value and the first lower limit value, the second lower limit value is less than the first lower limit value, and an intersection area between the first virtual area and the second virtual area is larger than a predetermined area.

10 . The detection method of claim 7 , wherein a third indicator of the indicators is displayed for indicating that the fault event exists in the equipment, in a condition that both of the second upper limit value and the second lower limit value are less than the first lower limit value.

11 . A computer-implemented method for detecting a fault event, comprising:

aligning, by a processor, first data with second data at a plurality of steps, wherein the first data and the second data are associated with equipment for fabricating semiconductor devices;

converting, by the processor, the first data and the second data into a first virtual area that is associated with the first data and a second virtual area that is associated with the second data;

comparing the first virtual area with the second virtual area; and

displaying, by an input/output (I/O) module, a result of comparing the first virtual area and the second virtual area via a plurality of indicators, in order to distinguish whether the fault event exists in the equipment.

12 . The computer-implemented method of claim 11 , wherein the first data and the second data are gathered at each of the steps.

13 . The computer-implemented method of claim 11 , wherein the operation of converting the first data and the second data comprises:

determining a first upper limit value and a first lower limit value according to the first data;

generating the first virtual area according to the first upper limit value and the first lower limit value;

determining a second upper limit value and a second lower limit value according to the second data; and

generating the second virtual area according to the second upper limit value and the second lower limit value.

14 . The computer-implemented method of claim 13 , wherein the first upper limit value is a predetermined times as large as a maximum value of the first data, and the first lower limit value is the predetermined times as large as a minimum value of the first data.

15 . The computer-implemented method of claim 13 , wherein the second upper limit value is predetermined times as large as a maximum value of the second data, and the second lower limit value is the predetermined times as large as a minimum value of the second data.

16 . The computer-implemented method of claim 11 , wherein the operation of comparing the first virtual area with the second virtual area:

comparing, by the processor, the first upper limit value and the first lower limit value with the second upper limit value and the second lower limit value.

17 . The computer-implemented method of claim 16 , wherein the operation of the displaying the result of comparing the first virtual area and the second virtual area comprises:

displaying a first indicator of the indicators to indicate that there is no fault event, in a condition that the second upper limit value is less than the first upper limit value, and the second lower limit value is greater than the first lower limit value.

18 . The computer-implemented method of claim 17 , further comprises:

displaying a second indicator of the indicators to indicate that the fault event exists in the equipment, in a condition that the second upper limit value is between the first upper limit value and the first lower limit value, the second lower limit value is less than the first lower limit value, and an intersection area between the first virtual area and the second virtual area is larger than a predetermined area.

19 . The computer-implemented method of claim 18 , further comprises:

displaying a third indicator of the indicators to indicate that the fault event exists in the equipment, in a condition that both of the second upper limit value and the second lower limit value are less than the first lower limit value.

20 . The computer-implemented method of claim 11 , wherein the indicators are displayed with different color patterns.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2016
From: HSUEH, YUEH-CHENG; LIU, YU-WEI; LEE, LIANG-LUN; LIN, TZU-CHIANG; CHEN, CHUN-YU; LIU, CHIA-HUNG
To: INOTERA MEMORIES, INC.
Reel/Frame 040068/0790 →