Process using oxide supporter for manufacturing a capacitor lower electrode of a micro stacked DRAM
View Patent ↗A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM is disclosed. First, form a stacked structure. Second, form a photoresist layer on an upper oxide layer and then etch them. Third, deposit a polysilicon layer onto the upper oxide layer and the nitride layer. Fourth, deposit a nitrogen oxide layer on the polysilicon layer and the upper oxide layer. Sixth, partially etch the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias. Seventh, oxidize the polysilicon layer to form a plurality of silicon dioxides surround the vias. Eighth, etch the nitride layer, the dielectric layer and the lower oxide layer beneath the vias. Ninth, form a metal plate and a capacitor lower electrode in each of the vias. Tenth, etch the nitrogen oxide layer, the polysilicon layer, the nitride layer and the dielectric layer.
1. A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM, comprising:
forming a stacked structure on a semiconductor substrate, wherein the semiconductor substrate has a plurality of conductor plugs, the stacked structure includes an upper oxide layer, a lower oxide layer, a dielectric layer, and a nitride layer, the dielectric layer and the nitride layer are between the upper oxide layer and the lower oxide layer, the nitride layer is on the dielectric layer;
forming a photoresist layer on the upper oxide layer, partially etching the photoresist layer and the upper oxide layer;
depositing a polysilicon layer on the upper oxide layer and the nitride layer;
depositing a nitrogen oxide layer on the polysilicon layer and the upper oxide layer;
partially etching the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias;
oxidizing the polysilicon layer converting the polysilicon layer to silicon dioxide surrounding the vias;
etching the nitride layer, the dielectric layer and the lower oxide layer beneath the vias;
forming a metal plate and a capacitor lower electrode in each of the vias; and
etching the nitrogen oxide layer, the polysilicon layer, certain portions of the nitride layer and the dielectric layer under the nitride layer in turn, wherein each of capacitor lower electrodes is surrounded and adhered with the silicon dioxide and the nitride layer to increase the supporting force, reduce the difficulty of disposing a capacitor dielectric layer and a capacitor upper electrode onto the capacitor lower electrode, and prevent toppling of the capacitor lower electrode.
2. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 1 , wherein during partially etching the photoresist layer and the upper oxide layer, the photoresist layer and the upper oxide layer in an array area are etched first, and then the photoresist layer in a peripheral area is etched.
3. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 1 , wherein before depositing a nitrogen oxide layer on the polysilicon layer and the upper oxide layer, further comprises polishing the polysilicon layer by chemical mechanical polishing to make it and the upper oxide layer have the same level.
4. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 1 , wherein during forming the vias, the vias are located via a photolithography process and a plasma etching process.
5. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 1 , wherein during oxidizing the polysilicon layer, the silicon dioxides are formed via an annealing process.
6. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 1 , wherein during etching the nitride layer, the dielectric layer and the lower oxide layer under the vias, the nitride layer, the dielectric layer and the lower oxide layer out of the vias are reserved.
7. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 1 , wherein before etching the dielectric layer under the nitride layer, further comprises forming a moat in the peripheral area to prevent from etching.
8. A process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM, comprising:
forming a stacked structure, wherein the stacked structure includes an upper oxide layer, a lower oxide layer, a dielectric layer, and a nitride layer, the dielectric layer and the nitride layer are between the upper oxide layer and the lower oxide layer, the nitride layer is on the dielectric layer;
forming a photoresist layer on the upper oxide layer, partially etching the photoresist layer and the upper oxide layer;
depositing a polysilicon layer on the upper oxide layer and the nitride layer;
depositing a nitrogen oxide layer on the polysilicon layer and the upper oxide layer;
partially etching the nitrogen oxide layer, the polysilicon layer and the upper oxide layer to form a plurality of vias;
oxidizing the polysilicon layer converting the polysilicon layer to silicon dioxide surrounding the vias;
etching the nitride layer, the dielectric layer and the lower oxide layer beneath the vias;
forming a capacitor lower electrode in each of the vias; and
etching the nitrogen oxide layer, the polysilicon layer, certain portions of the nitride layer and the dielectric layer beneath the nitride layer in turn, wherein each of capacitor lower electrodes is surrounded and adhered with the silicon dioxide and the nitride layer to increase the supporting force, the difficulty of disposing a capacitor dielectric layer and a capacitor upper electrode onto the capacitor lower electrode is improved, and prevent toppling of the capacitor lower electrode.
9. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 8 , wherein during partially etching the photoresist layer and the upper oxide layer, the photoresist layer and the upper oxide layer in an array area are etched first, and then the photoresist layer in a peripheral area is etched.
10. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 8 , wherein before depositing a nitrogen oxide layer on the polysilicon layer and the upper oxide layer, further comprises polishing the polysilicon layer by chemical mechanical polishing to make it and the upper oxide layer have the same level.
11. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 8 , wherein during forming the vias, the vias are located via a photolithography process and a plasma etching process.
12. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 8 , wherein during oxidizing the polysilicon layer, the silicon dioxides are formed via an annealing process.
13. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 8 , wherein during etching the nitride layer, the dielectric layer and the lower oxide layer beneath the vias, the nitride layer, the dielectric layer and the lower oxide layer out of the vias are reserved.
14. The process using oxide supporter for manufacturing a capacitor lower electrode of a micron stacked DRAM as claimed in claim 8 , wherein before etching the dielectric layer beneath the nitride layer, further comprises forming a moat in the peripheral area to prevent from etching.