Method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning
View Patent ↗A method for making a semiconductor device includes forming a first mask pattern on a device layer, forming a second mask pattern on the first mask pattern, etching the device layer not covered by the first and second mask patterns to thereby form a first trench, trimming the first mask pattern to form an intermediate mask pattern, depositing a material layer to fill the first trench, polishing the material layer to expose a top surface of the intermediate mask pattern, removing the intermediate mask pattern to form an opening, etching the device layer through the opening to thereby form a second trench.
1. A method for fabricating fine patterns of semiconductor device utilizing self-aligned double patterning, comprising:
providing a device layer;
forming a first mask pattern on the device layer;
forming a second mask pattern on the first mask pattern, wherein the second mask pattern partially covers the first mask pattern;
selectively etching the device layer not covered by the first and second mask patterns to thereby form a first trench therein;
after forming the first trench, removing the first mask pattern not covered by the second mask pattern to form an intermediate mask pattern;
depositing a mask material layer to fill the first trench and cover the intermediate mask pattern;
polishing the mask material layer to expose a top surface of the intermediate mask pattern, thereby forming a third mask pattern;
selectively removing the intermediate mask pattern to form an opening; and
etching the device layer through the opening to thereby form a second trench.
2. The method according to claim 1 wherein the device layer is a dielectric layer.
3. The method according to claim 2 wherein the dielectric layer comprises silicon oxide.
4. The method according to claim 1 wherein the device layer is a semiconductor substrate.
5. The method according to claim 4 wherein the semiconductor substrate comprises silicon substrate.
6. The method according to claim 1 wherein the device layer is a multi-layer stack structure.
7. The method according to claim 6 wherein the multi-layer stack structure comprises polysilicon-tungsten-silicon nitride stack structure.
8. The method according to claim 1 wherein the first mask pattern comprises polysilicon.
9. The method according to claim 1 wherein the second mask pattern comprises carbon.
10. The method according to claim 1 wherein the second mask pattern comprises amorphous carbon.
11. The method according to claim 1 wherein the mask material layer and the second mask pattern are composed of the same material.
12. The method according to claim 1 wherein the mask material comprises carbon or amorphous carbon.
13. The method according to claim 1 wherein the first mask pattern comprises a plurality of dense line patterns.
14. The method according to claim 13 wherein line width to space ratio (L:S) of the plurality of dense line patterns is 1:1.
15. The method according to claim 1 wherein an anti-reflection coating layer is provided on the second mask pattern.
16. The method according to claim 1 wherein after forming the second mask pattern on the first mask pattern, the first mask pattern and the second mask pattern together form an etching hard mask with a step structure.