Methods of fabricating a semiconductor package structure including at least one redistribution layer
View Patent ↗A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.
1. A method for fabricating a semiconductor package structure, comprising:
forming a plurality of redistribution layers comprising a metal layer and a block layer over the metal layer, the metal layer formed over a first carrier and including a dielectric layer and metal segments disposed in the dielectric layer;
forming first connectors directly on a first side of the plurality of redistribution layers;
connecting the first side of the plurality of redistribution layers to a second carrier using the first connectors, and removing the first carrier;
forming second connectors directly on a second side opposite the first side of the plurality of redistribution layers;
connecting the second side of the plurality of redistribution layers to at least one chip using the second connectors, and subsequently removing the second carrier; and
connecting the first side of the plurality of redistribution layers to a substrate using the first connectors.
2. The method of claim 1 , further comprising:
forming a temporary adhesive over the at least one chip prior to removing the second carrier; and
removing the temporary adhesive after connecting the first side of the plurality of redistribution layers to the substrate.
3. The method of claim 1 , wherein forming the plurality of redistribution layers comprises forming the metal layer using a damascene process.
4. The method of claim 1 , wherein forming each of the plurality of redistribution layers comprises:
depositing the dielectric layer;
etching the dielectric layer to form a plurality of openings; and
filling the openings with a metal material to form the metal segments.
5. The method of claim 1 , wherein forming the first connectors comprises interposing the first connectors between segments of the block layer and connecting the first connectors to the metal layer.
6. The method of claim 1 , further comprising forming a passivation layer between a first redistribution layer of the plurality of redistribution layers and the first connectors.
7. A method of manufacturing a semiconductor device package, the method comprising:
positioning at least one redistribution layer over a first carrier;
attaching first connectors on a first side of the at least one redistribution layer, opposite the first carrier;
attaching a second carrier on the first side of the at least one redistribution layer, and removing the first carrier;
attaching second connectors on a second, opposite side of the at least one redistribution layer;
attaching at least one chip to the second, opposite side of the at least one redistribution layer, and subsequently removing the second carrier;
attaching the first side of the at least one redistribution layer to a substrate; and
operatively coupling the at least one chip to the substrate through the at least one redistribution layer.
8. The method of claim 7 , further comprising forming the at least one redistribution layer, comprising:
forming a dielectric layer over the first carrier;
forming a metal layer over the dielectric layer; and
forming a block layer over the metal layer.
9. The method of claim 8 , further comprising forming a first passivation layer over the first carrier prior to forming the dielectric layer.
10. The method of claim 9 , further comprising:
forming a second passivation layer over an uppermost block layer;
removing portions of the second passivation layer and the uppermost block layer to expose portions of an uppermost metal layer prior to attaching the first connectors on the first side of the at least one redistribution layer.
11. The method of claim 10 , further comprising forming an adhesive layer between the second passivation layer and the second carrier.
12. The method of claim 8 , wherein forming the metal layer further comprises:
removing portions of the dielectric layer to form a plurality of openings; and
filling the plurality of openings with a metal material to form a plurality of metal segments.
13. The method of claim 8 , wherein forming the metal layer comprises forming the metal layer using at least one of a single-damascene process or a dual-damascene process.
14. The method of claim 8 , further comprising forming a plurality of vias through the block layer, such that the metal segments of different metal layers are connected by the plurality of vias.
15. The method of claim 7 , further comprising:
forming a temporary adhesive over the at least one chip prior to removing the second carrier; and
separating individual chips prior to attaching the first side of the at least one redistribution layer to the substrate.
16. The method of claim 7 , wherein operatively connecting the at least one chip to the substrate through the at least one redistribution layer comprises:
forming the first connectors directly on the first side of the at least one redistribution layer; and
forming the second connectors directly on the second side of the at least one redistribution layer.