IP Library Granted Patent US 9,735,161
Granted Patent B2
US 9,735,161 · App. 14/848,357 · Granted Aug 15, 2017

Memory device and fabricating method thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,735,161
App. No.
14/848,357
Granted
Aug 15, 2017
Kind
B2
Abstract

A memory device and a method for fabricating the same are provided. The memory device includes a substrate, a first active region, a second active region, a gate structure, and a capping layer. The first active region and the second active region are alternately disposed in the substrate. The gate structure is disposed in the substrate and between the first active region and the second active region. The capping layer is over the gate structure to define a void therebetween.

Claims (39)

1. A method for fabricating a memory device, the method comprising:

forming a first active region and a second active region mutually laterally spaced in a substrate;

forming a gate structure in the substrate and between the first active region and the second active region; and

forming a capping layer over the gate structure and sealing a space between the gate structure and the capping layer to define a void, comprising:

forming a sacrificial structure over the gate structure;

forming a first part of the capping layer over the sacrificial structure, the first part of the capping layer having an opening therethrough;

removing the sacrificial structure; and

forming a second part of the capping layer in the opening to complete the capping layer and define the void.

2. The method of claim 1 , wherein forming the gate structure comprises:

forming a first portion; and

forming a second portion embedded in the first portion.

3. The method of claim 1 , wherein forming the capping layer comprises making the capping layer of an oxide.

4. The method of claim 1 , wherein forming the first part of the capping layer comprises:

depositing a capping liner over the sacrificial structure; and

etching the capping liner to form the first part of the capping layer having the opening.

5. The method of claim 1 , wherein forming the sacrificial structure comprises making the sacrificial structure of a nitride or a photoresist.

6. The method of claim 1 , wherein removing the sacrificial structure is performed by wet etching or photoresist stripping.

7. The method of claim 1 , wherein forming the first part of the capping layer comprises making the first part of the capping layer of an oxide, and wherein forming the second part of the capping layer comprises making the second part of the capping layer of a nitride.

8. The method of claim 1 , further comprising depositing a nitride layer over the capping layer.

9. A memory device, comprising:

a substrate;

a first active region and a second active region mutually laterally spaced in the substrate;

a recess extending between the first active region and the second active region and into at least a portion of the substrate;

a gate structure at least partially located in the recess of the substrate and between the first active region and the second active region; and

a capping layer located vertically over the gate structure, the capping layer bridging sidewalls of the recess and sealing a space between the gate structure and the capping layer to define a sealed void.

10. The memory device of claim 9 , wherein the sealed void is a vacuum.

11. The memory device of claim 9 , wherein the capping layer is made of an oxide.

12. The memory device of claim 9 , further comprising a nitride layer over the capping layer.

13. The memory device of claim 9 , wherein sidewalls of the recess contain a liner.

14. The memory device of claim 9 , wherein the gate structure is a single-layer structure or a multi-layer structure.

15. The memory device of claim 14 , wherein the gate structure is a multi-layer structure comprising:

a first portion; and

a second portion embedded in the first portion.

16. The memory device of claim 9 , wherein the sealed void contains a gaseous material.

17. The memory device of claim 16 , wherein the gaseous material has a dielectric constant of about 1.

18. The memory device of claim 9 , wherein the capping layer comprises:

a first part; and

a second part interposing the first part.

19. The memory device of claim 18 , wherein the first part of the capping layer is made of an oxide, and the second part of the capping layer is made of a nitride.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2015
From: WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 036537/0601 →