Dynamic random access memory unit and fabrication method thereof
View Patent ↗A dynamic random access memory unit includes a substrate having a trench disposed therein, a self-aligned trench isolation structure formed in the bottom portion of the trench, and a first trenched gate formed in the bottom portion of the trench and above the self-aligned trench isolation structure. The substrate includes at least one pillar-shaped active body having a drain region, a body region atop the drain region, and a source region atop the body region. The first trenched gate includes a first spacer formed on the side-wall in the bottom portion of the trench to selectively cover and surround the portion of the side-wall in the trench that comprises the drain region, such for defining the width of the self-aligned trench isolation structure.
1. A dynamic random access memory unit, comprising:
a substrate, including at least one pillar-shaped active body and having a trench disposed in the substrate,
wherein the pillar-shaped active body has a drain region of a first conductivity type, a body region of a second conductivity type opposite to the first conductivity type, and a source region of the first conductivity type,
wherein the body region is arranged atop the drain region and the source region is arranged atop the body region;
a self-aligned trench isolation structure, formed in the bottom portion of the trench; and
a first trenched gate, formed in the bottom portion of the trench and above the self-aligned trench isolation structure,
wherein the first trenched gate includes a first spacer,
wherein the first spacer is formed on the side-wall in the bottom portion of the trench to selectively cover and surround the portion of the side-wall in the trench that comprises the drain region, such for defining the width of the self-aligned trench isolation structure.
2. The dynamic random access memory unit of claim 1 , wherein the side-surface of the self-aligned trench isolation structure is flush with the side-surface of the first spacer.
3. The dynamic random access memory unit of claim 1 , wherein the self-aligned trench isolation structure includes an oxide liner, a silicon nitride liner, a spin-on dielectric layer, and a high-density plasma layer.
4. The dynamic random access memory unit of claim 1 , wherein the first trenched gate further includes a first conductive layer, the first conductive layer selectively covers the surface of the first spacer, and the dynamic random access memory unit further comprises:
a second trenched gate, formed in the upper portion of the trench,
wherein the second trenched gate includes a second spacer formed on the side-wall in the upper portion of the trench to selectively cover and surround the portion of the side-wall in the trench that comprises the source region, the body region, and the portion of the drain region adjacent to the body region; and
a gate dielectric layer, covering the side-wall in the upper portion of the trench and arranged between the second trenched gate and the pillar-shaped active body.
5. The dynamic random access memory unit of claim 4 , wherein the second trenched gate further includes a second conductive layer selectively covering the surface of the second spacer and forming a crossing pattern with the first conductive layer, the first conductive layer extends along a first direction, and the second conductive layer extends along a second direction.
6. The dynamic random access memory unit of claim 5 , further including a first cover layer formed in the trench to cover the first trenched gate and arranged between the first trenched gate and the second trenched gate.
7. The dynamic random access memory unit of claim 6 , further including:
a second cover layer, covering the second trenched gate;
a conductive pad, formed on the pillar-shaped active body; and
a stacked capacitor structure, formed on the conductive pad.
8. A dynamic random access memory unit, comprising:
a pillar-shaped active body, having a drain region of a first conductivity type, a body region of a second conductivity type, and a source region of the first conductivity type,
wherein the body region is arranged atop the drain region, and the source region is arranged atop the body region;
a first trenched gate, including a first spacer,
wherein the first spacer selectively surrounds the portion of the pillar-shaped active body that comprises the drain region;
a second trenched gate, including a second spacer,
wherein the second spacer selectively surrounds the portion of the pillar-shaped active body that comprises the body region, the portion of the source region adjacent to the body region, and the portion of the drain region adjacent to the body region; and
a gate dielectric layer, arranged between the second trenched gate and the pillar-shaped active body.
9. The dynamic random access memory unit of claim 8 , wherein the first trenched gate further includes a first conductive layer selectively covering the surface of the first spacer, the second trenched gate further includes a second conductive layer selectively covering the surface of the second spacer and forming a crossing pattern with the first conductive layer, the first conductive layer extends along a first direction, and the second conductive layer extends along a second direction.