IP Library Granted Patent US 9,472,664
Granted Patent B1
US 9,472,664 · App. 14/803,100 · Granted Oct 18, 2016

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 9,472,664
App. No.
14/803,100
Granted
Oct 18, 2016
Kind
B1
Abstract

The present disclosure provides a semiconductor device including a substrate, a gate structure, a channel layer, a first active region and a second active region. The gate structure is disposed in the substrate. The channel layer is sandwiched between the gate structure and the substrate. A material of the channel layer is selected from the group consisting of silicon-germanium epitaxial material, silicon-carbon epitaxial material, and a combination thereof. The first active region and the second active region are disposed in the substrate and respectively disposed at opposite sides of the gate structure. A method for manufacturing a semiconductor device is provided herein.

Claims (22)

1. A semiconductor device, comprising:

a substrate;

a gate structure disposed in the substrate;

a channel layer sandwiched between the gate structure and the substrate, wherein a material of the channel layer is selected from the group consisting of silicon-germanium epitaxial material, silicon-carbon epitaxial material, and a combination thereof, and the content of germanium, carbon or the both of the channel layer is abruptly or gradually increased from a side of the channel layer contacting the substrate to another side of the channel layer contacting the gate structure; and

a first active region and a second active region disposed in the substrate and respectively disposed at opposite sides of the gate structure.

2. The semiconductor device of claim 1 , wherein the content of germanium, carbon or the both of the channel layer has a maximum between a side of the channel layer contacting the substrate and another side of the channel layer contacting the gate structure.

3. The semiconductor device of claim 1 , wherein a memory cell comprises the first active region, the gate structure, and the second active region.

4. The semiconductor device of claim 3 , further comprising a plurality of isolation structures disposed in the substrate, and the memory cell disposed between adjacent two of the isolation structures.

5. The semiconductor device of claim 4 , further comprising an epitaxial layer disposed between each of the isolation structures and the substrate.

6. The semiconductor device of claim 5 , wherein a material of the epitaxial layer is consisting essentially of silicon-germanium epitaxial material, silicon-carbon epitaxial material, or silicon-carbon-germanium epitaxial material.

7. The semiconductor device of claim 6 , wherein the materials of the epitaxial layer and the channel layer are individually Si1-xGex, 0<x≦0.8; Si1-yCy, 0<y≦0.3; or Si1-a-bGeaCb, 0<a≦0.8, 0<b≦0.3.

8. The semiconductor device of claim 6 , wherein the content of germanium, carbon or the both of the epitaxial layer is abruptly or gradually increased from a side of the epitaxial layer contacting one of the isolation structures to another side of the epitaxial layer contacting the substrate.

9. The semiconductor device of claim 6 , wherein the content of germanium, carbon or the both of the epitaxial layer has a maximum between a side of the epitaxial layer contacting one of the isolation structures and another side of the epitaxial layer contacting the substrate.

10. A semiconductor device, comprising:

a substrate;

a gate structure disposed in the substrate;

an active region disposed in the substrate and disposed at a side of the gate structure;

an isolation structure disposed in the substrate and disposed between two adjacent of the active regions; and

an epitaxial layer overlying a surface of the isolation structure, wherein a material of the epitaxial layer is selected from the group consisting of silicon-germanium, silicon-carbon, and a combination thereof.

11. The semiconductor device of claim 10 , wherein the materials of the epitaxial layer and the channel layer are individually Si1-xGex, 0<x≦0.8; Si1-yCy, 0<y≦0.3; or Si1-a-bGeaCb, 0<a≦0.8, 0<b≦0.3.

12. The semiconductor device of claim 10 , wherein the content of germanium, carbon or the both of the epitaxial layer is abruptly or gradually increased from a side of the epitaxial layer contacting one of the isolation structures to another side of the epitaxial layer contacting the substrate.

13. The semiconductor device of claim 10 , wherein the content of germanium, carbon or the both of the epitaxial layer has a maximum between a side of the epitaxial layer contacting one of the isolation structures and another side of the epitaxial layer contacting the substrate.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 20, 2015
From: WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 036130/0445 →