Vertical PMOS field effect transistor and manufacturing method thereof
View Patent ↗A PMOS field effect transistor includes a substrate, a first nitride layer, a mesa structure, two gate oxide films, a gate stack layer and a second nitride layer. The substrate has a oxide layer and a first doping area. The first nitride layer is located on the oxide layer. The mesa structure includes a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer. The first strained Si—Ge layer is located on the oxide layer and the first nitride layer. The epitaxial Si layer is located on the first strained Si—Ge layer. The second strained Si—Ge layer is located on the epitaxial Si layer. In the surface layer of the second strained Si—Ge layer, there is a second doping area. The two gate oxide films are located at two sides of the mesa structure.
1. A PMOS field effect transistor, comprising:
a substrate having an oxide layer and a first doping area;
a first nitride layer located on the oxide layer, wherein the first nitride layer and the oxide layer have a substrateconcave trough that corresponds to the first doping area;
a mesa structure having a first strained Si—Ge layer, an epitaxial Si layer and a second strained Si—Ge layer, wherein the first strained Si—Ge layer is located on the oxide layer and the first nitride layer, the epitaxial Si layer is located on the first strained Si—Ge layer, the second strained Si—Ge layer is located on the epitaxial Si layer, and there is a second doping area in the surface layer of the second strained Si—Ge layer;
two gate oxide films located at two sides of the mesa structure;
a gate stack layer located at two sides of the mesa structure and the first oxide layer; and
a second nitride layer at two sides of the mesa structure and the gate stack layer.
2. The PMOS field effect transistor as claimed in claim 1 , wherein the substrate is a N-typed Si substrate.
3. The PMOS field effect transistor as claimed in claim 1 , wherein the first strained Si—Ge layer has a graded doping concentration.
4. The PMOS field effect transistor as claimed in claim 1 , wherein the second strained Si—Ge layer has a graded doping concentration.
5. The PMOS field effect transistor as claimed in claim 1 , wherein the gate stack layer is composed of poly-silicon.
6. The PMOS field effect transistor as claimed in claim 1 , wherein the first nitride layer is composed of nitride silicon.
7. The PMOS field effect transistor as claimed in claim 1 , wherein the second nitride layer is composed of nitride silicon.
8. The PMOS field effect transistor as claimed in claim 1 , wherein the first doping area is used as a source, and the second doping area is used as a drain.