IP Library Granted Patent US 9,053,928
Granted Patent B2
US 9,053,928 · App. 14/198,783 · Granted Jun 9, 2015

Wafer and film coating method of using the same

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Quick Facts
Patent No.
US 9,053,928
App. No.
14/198,783
Granted
Jun 9, 2015
Kind
B2
Abstract

The present disclosure provides a wafer that can be used in coating films. The wafer includes a front surface, a back surface opposite to the front surface, and a plurality of trenches. The back surface further includes a central region and a surrounding region. The trenches are disposed on the back surface. The spacing between any two adjacent trenches in surrounding region is less than the spacing between any two adjacent trenches in the central region.

Claims (30)

1. A first wafer, utilized in vapor deposition process for depositing films on a second wafer having an active side, comprising:

a right side;

a back side corresponding to the right side and face to the active side of the second wafer, comprising a central region and a surrounding region around the central region; and

a plurality of trenches existing on the back side, wherein the spacing between any two of the adjacent trenches inside the surrounding region is smaller than the spacing between any two of the adjacent trenches insides the central region, configured to increase the reaction area for a reaction gas in the surrounding region, whereby the thickness of each film on the active side of the second wafer corresponding to the surrounding region of the back side is decreased.

2. The first wafer of claim 1 , wherein the trenches are the circular trenches.

3. The first wafer of claim 1 , wherein the average distributed density of the trenches is increased from the central region to the surrounding region.

4. The first wafer of claim 1 , wherein the depth of the trenches are increased from the central region to the surrounding region.

5. The first wafer of claim 1 , wherein the depth of the trenches are the same.

6. A first wafer, utilized in vapor deposition process for depositing films on a silicon wafer having an active side, comprising:

a right side;

a back side corresponding to the right side and face to the active side of the silicon wafer, comprising a central region and a surrounding region around the central region; and

a plurality of trenches existing on the back side, wherein the average distributed density of the trenches in the surrounding region is greater than the average distributed density of the trenches in the central region, configured to increase the reaction area for a reaction gas in the surrounding region, whereby the thickness of each film on the active side of the silicon wafer corresponding to the surrounding region of the back side is decreased.

7. The first wafer of claim 6 , wherein the trenches are the circular trenches.

8. The first wafer of claim 7 , wherein the spacing between any two adjacent trenches inside the surrounding region is smaller than the spacing between any two adjacent trenches insides the central region.

9. The first wafer of claim 6 , wherein the average density of the trenches is increased from the central region to the surrounding region.

10. The first wafer of claim 6 , wherein the depth of the trenches are increased from the central region to the surrounding region.

11. The first wafer of claim 6 , wherein the depth of the trenches are the same.

12. A wafer coating method, comprising:

providing a reactor, the reactor comprising an inlet and an outlet;

placing at least a first wafer and a plurality of second wafers into the reactor, the first wafer and the second wafer are arranged along the first axial,

wherein the first wafer comprises a first right side, a first back side corresponding to the first right side and a plurality of trenches, the first back side comprises a central region and a surrounding region, and the trenches are on the first back side,

wherein each of the second wafers comprises a second right side and a second back side corresponding to the second right side, and the second right side face to the first back side,

wherein the spacing between two adjacent trenches inside the surrounding region is smaller than the spacing between two adjacent trenches inside the central region; and

introducing a reacting gas from the inlet to the reactor, wherein the first wafer is configured to increase the reaction area for the reaction gas in the surrounding region, whereby the thickness of a film formed on the second right side of the second wafer is decreased.

13. The wafer coating method of claim 12 , wherein the first wafer is deposing between two adjacent second wafers.

14. The wafer coating method of claim 12 , wherein the trenches are circular trenches.

15. The wafer coating method of claim 12 , wherein the average distributed density of the trenches in the surrounding region is greater than the average distributed density of the trenches in the central region.

16. The wafer coating method of claim 12 , wherein the depth of the trenches are increased from the central region to the surrounding region.

17. The wafer coating method of claim 12 , wherein the depth of the trenches are the same.

18. The wafer coating method of claim 12 , wherein the average distributed density of the trenches is increased from the central region to the surrounding region.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2014
From: LAHAUG, ERIC; YANG, CHIA-MING; TSUI, REGAN STANLEY
To: INOTERA MEMORIES, INC.
Reel/Frame 032398/0629 →