IP Library Granted Patent US 8,901,660
Granted Patent B2
US 8,901,660 · App. 13/081,567 · Granted Dec 2, 2014

Semiconductor structure and fault location detecting system

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,901,660
App. No.
13/081,567
Granted
Dec 2, 2014
Kind
B2
Abstract

A semiconductor structure includes a grounding unit, a P-type substrate, a P-type well area, an NMOS structure, a P-type well contact area, a shallow trench isolation structure, and a charge guiding groove. The P-type substrate is formed above the grounding unit. The P-type well area is formed on the P-type substrate. The NMOS structure is formed on the P-type well area, and the NMOS structure includes at least one exposed N-type source area, at least one exposed N-type drain area, and at least one exposed N-type gate area. The P-type well contact area is formed on the P-type well area. The shallow trench isolation structure is disposed between the NMOS structure and the P-type well contact area. The charge guiding groove passes through the P-type well contact area and one part of the P-type well area and is electrically connected with the grounding unit.

Claims (4)

1. A fault location detecting system, comprising:

a semiconductor structure comprising at least one P-type substrate, at least one N-type doping area, at least one P-type well area, at least one NMOS structure, at least one P-type well contact area, and at least one charge guiding groove, wherein the N-type doping area is formed on the P-type substrate, the P-type well area is formed on the N-type doping area, the NMOS structure is formed on the P-type well area, the NMOS structure includes at least one exposed N-type source area, at least one exposed N-type drain area, and at least one exposed N-type gate area disposed between the N-type source area and the N-type drain area, the P-type well contact area is formed on the N-type doping area, and the charge guiding groove passes through the P-type well contact area and one part of the N-type doping area and is disposed between the P-type well area and the P-type well contact area;

an ion beam generating device disposed above the semiconductor structure, wherein at least one ion beam generated by the ion beam generating device is projected onto the semiconductor structure to form an ion layer with positive charges and trigger off a plurality of reflected surface electronic signals, the positive charges of the ion layer are formed on the top surface of NMOS structure and the inner surface of the charge guiding groove, and the positive charges of the ion layer are transmitted to the N-type doping area through the charge guiding groove; and

an image capturing device disposed above the semiconductor structure to receive the reflected surface electronic signals.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2011
From: WANG, WEI CHIH
To: INOTERA MEMORIES, INC.
Reel/Frame 026088/0937 →