IP Library Granted Patent US 8,455,363
Granted Patent B2
US 8,455,363 · App. 13/282,593 · Granted Jun 4, 2013

Method for adjusting trench depth of substrate

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Quick Facts
Patent No.
US 8,455,363
App. No.
13/282,593
Granted
Jun 4, 2013
Kind
B2
Abstract

A method for adjusting the trench depth of a substrate has the steps as follows. Forming a patterned covering layer on the substrate, wherein the patterned covering layer defines a wider spacing and a narrower spacing. Forming a wider buffering layer arranged in the wider spacing and a narrower buffering layer arranged in the narrower spacing. The thickness of the narrower buffering layer is thinner than the wider buffering layer. Implementing dry etching process to make the substrate corresponding to the wider and the narrower buffering layers form a plurality of trenches. When etching the wider and the narrower buffering layers, the narrower buffering layer is removed firstly, so that the substrate corresponding to the narrower buffering layer will be etched early than the substrate corresponding to the wider buffering layer.

Claims (6)

1. A method for adjusting the trench depth of a semiconductor substrate, comprising the steps of:

forming a patterned covering layer on a substrate to define an alternatively arranged wider spacing and narrower spacing, the patterned covering layer being formed by forming a covering layer on the substrate and then a patterned photoresist layer thereon, exposed portions of the covering layer being etched to form the patterned covering layer, the covering layer including a hard mask layer disposed on the substrate, an oxide layer disposed on the hard mask layer, and a carbonic layer disposed on the oxide layer;

forming a wider buffering layer in the wider spacing and a narrower buffering layer in the narrower spacing, wherein the thickness of the narrower buffering layer is thinner than the wider buffering layer;

executing a dry etching process to etch the wider and the narrower buffering layers to respectively form a wider trench and a narrower trench by firstly using halogen hydride gas, upon the narrower buffering layer is removed, replacing the halogen hydride gas by fluorocarbon gas for adjusting selective ratio, so that the portion of the substrate corresponding to the narrower buffering layer is etched earlier than the portion of the substrate corresponding to the wider buffering layer, wherein the portion of the substrate corresponding to the narrower is etched to a predetermined depth when the wider buffering layer is removed; and

terminating the dry etching process when the depth of the wider trench approximately equals to the depth of the narrower trench.

2. The method as claimed in claim 1 , wherein the material of the hard mask layer is at least one of silicon nitride and oxynitride (SiON).

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2011
From: LEE, TZUNG HAN; HUANG, CHUNG-LIN
To: INOTERA MEMORIES, INC.
Reel/Frame 027137/0521 →