Method for fabricating semiconductor device

1. A method for fabricating a semiconductor device, comprising:

providing a substrate;

defining a first active region and a second active region in the substrate;

forming an electrode on the substrate, covering the first active region and the second active region;

forming a first sacrificial layer on the second active layer and performing a first doping process to a portion of the electrode to form a first work function electrode on the first active layer;

removing the first sacrificial layer and forming a second sacrificial layer on the first active layer, and performing a second doping process to a portion of the electrode to form a second work function electrode on the second active layer;

removing the second sacrificial layer, and etching a portion of the first work function electrode and the second work function electrode to form a patterned first work function electrode with a first bulge portion and a patterned second work function electrode with a second bulge portion, wherein the patterned first and second work function electrodes further comprise flat portions over the first active region and the second active region of the substrate;

forming a hard mask layer, covering the first bulge portion and the second bulge portion and extending to cover the flat portions of the patterned first and second work function electrodes;

forming a third sacrificial layer on the second active region, covering the patterned second work function electrode;

removing a portion of the patterned first work function electrode to leave the first bulge portion under the hard mask layer to be a first work function gate structure using the third sacrificial layer covering the patterned second work function electrode as a first etching mask;

removing the third sacrificial layer and forming a fourth sacrificial layer on the first active region, covering the patterned first work function electrode;

removing a portion of the patterned second work function electrode to leave the second bulge portion under the hard mask layer to be a second work function gate structure using the fourth sacrificial layer covering the patterned first work function electrode as a second etching mask; and

removing the fourth sacrificial layer.

2. The method for fabricating the semiconductor device as claimed in claim 1 , wherein the first sacrificial layer, the second sacrificial layer, the third sacrificial layer, or the fourth sacrificial layer comprises oxide, nitride, or oxynitride.

3. The method for fabricating the semiconductor device as claimed in claim 1 , wherein the first bulge portion of the first work function gate structure has a first bottom width, and the first bottom width is equal to or smaller than a width of the hard mask layer.

4. The method for fabricating the semiconductor device as claimed in claim 1 , wherein the second bulge portion of the second work function gate structure has a second bottom width, and the second bottom width is equal to or smaller than a width of the hard mask layer.

5. The method for fabricating the semiconductor device as claimed in claim 1 , further comprising:

patterning the first sacrificial layer on the second active region by using a first mask; and

patterning the second sacrificial layer on the first active region by using a second mask.

6. The method for fabricating the semiconductor device as claimed in claim 5 , further comprising patterning the third sacrificial layer on the second active region by using the first mask.

7. The method for fabricating the semiconductor device as claimed in claim 6 , further comprising patterning the fourth sacrificial layer on the first active region by using the second mask.

8. The method for fabricating the semiconductor device as claimed in claim 1 , further comprising forming a dielectric layer on the substrate, covering the first active region and second active region.

9. The method for fabricating the semiconductor device as claimed in claim 1 , comprising forming a top electrode on the first bulge portion and the second bulge portion before forming the hard mask layer.

10. The method for fabricating the semiconductor device as claimed in claim 9 , wherein the top electrode comprises metal.

11. The method for fabricating the semiconductor device as claimed in claim 10 , wherein the metal comprises tungsten.

12. The method for fabricating the semiconductor device as claimed in claim 1 , wherein the hard mask layer comprises silicon nitride.

13. The method for fabricating the semiconductor device as claimed in claim 1 , wherein an etching rate of the first work function electrode is different from an etching rate of the second work function electrode.

14. The method for fabricating the semiconductor device as claimed in claim 1 , wherein the electrode comprises polysilicon.

15. The method for fabricating the semiconductor device as claimed in claim 13 , wherein the first work function electrode comprises N-type doped polysilicon.

16. The method for fabricating the semiconductor device as claimed in claim 15 , wherein the second work function electrode comprises P-type doped polysilicon.

17. The method for fabricating the semiconductor device as claimed in claim 16 , wherein the etching rate of the first work function electrode is faster than the etching rate of the second work function electrode.

18. A method for fabricating a semiconductor device, comprising:

providing a substrate;

defining a first active region and a second active region in the substrate;

forming an electrode on the substrate, covering the first active region and the second active region;

forming a first sacrificial layer on the second active layer by using a first mask and performing a first doping process to a portion of the electrode for forming a first work function electrode on the first active layer;

removing the first sacrificial layer and forming a second sacrificial layer on the first active layer by using a second mask, and performing a second doping process to a portion of the electrode for forming a second work function electrode on the second active layer;

removing the second sacrificial layer, and etching a portion of the first work function electrode and the second work function electrode for forming a patterned first work function electrode with a first bulge portion and a patterned second work function electrode with a second bulge portion, wherein the patterned first and second work function electrodes further comprise flat portions over the first active region and the second active region of the substrate;

forming a hard mask layer covering the first bulge portion and the second bulge portion and extending to cover the flat portions of the patterned first and second work function electrodes;

forming a third sacrificial layer on the second active region by using the first mask, covering the patterned second work function electrode;

removing a portion of the patterned first work function electrode to leave the first bulge portion under the hard mask layer to be a first work function gate structure using the third sacrificial layer covering the a portion of the patterned second work function electrode and the hard mask layer as a first etching mask;

removing the third sacrificial layer, and forming a fourth sacrificial layer on the first active region by using the second mask, covering the patterned first work function electrode;

removing a portion of the patterned second work function electrode to leave the second bulge portion under the hard mask layer to be a second work function gate structure using the fourth sacrificial layer covering the a portion of the patterned first work function electrode and the hard mask layer as a second etching mask; and

removing the fourth sacrificial layer.

19. The method for fabricating the semiconductor device as claimed in claim 18 , wherein the first bulge portion of the first work function gate structure has a first bottom width, and the first bottom width is equal to or smaller than a width of the hard mask layer.

20. The method for fabricating the semiconductor device as claimed in claim 18 , wherein the second bulge portion of the second work function gate structure has a second bottom width, and the second bottom width is equal to or smaller than a width of the hard mask layer.

21. The method for fabricating the semiconductor device as claimed in claim 18 , further comprising forming a top electrode on the first bulge portion and the second bulge portion before forming the hard mask layer.

22. The method for fabricating the semiconductor device as claimed in claim 21 , wherein the top electrode comprises metal.

23. The method for fabricating the semiconductor device as claimed in claim 22 , wherein the metal comprises tungsten.

24. The method for fabricating the semiconductor device as claimed in claim 18 , wherein the hard mask layer comprises silicon nitride.

25. The method for fabricating the semiconductor device as claimed in claim 18 , wherein an etching rate of the first work function electrode is different from an etching rate of the second work function electrode.