IP Library Granted Patent US 9,570,369
Granted Patent B1
US 9,570,369 · App. 15/068,649 · Granted Feb 14, 2017

Semiconductor package with sidewall-protected RDL interposer and fabrication method thereof

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Quick Facts
Patent No.
US 9,570,369
App. No.
15/068,649
Granted
Feb 14, 2017
Kind
B1
Abstract

A semiconductor package includes a redistributed layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side.

Claims (14)

1. A method for fabricating a semiconductor package, comprising:

providing a carrier;

forming a redistributed layer (RDL) interposer on the carrier;

mounting at least one semiconductor die on a first side of the RDL interposer;

cutting at least one cut trench penetrating through the RDL interposer, wherein the cut trench exposes a vertical sidewall of the RDL interposer;

molding the semiconductor die with a molding compound on the first side, wherein the molding compound fills into the cut trench and covers the vertical sidewall of the RDL interposer;

removing the carrier to expose a second side of the RDL interposer; and

forming a plurality of solder bumps or solder balls on the second side.

2. The method for fabricating a semiconductor package according to claim 1 , wherein the cut trench is cut along a dicing line.

3. The method for fabricating a semiconductor package according to claim 1 , wherein after removing the carrier, at least one protrudent feature is formed, wherein the protrudent feature protrudes from a surface on the second side.

4. The method for fabricating a semiconductor package according to claim 3 further comprising:

performing a planarization process to remove the protrudent feature.

5. The method for fabricating a semiconductor package according to claim 1 further comprising:

performing a wafer dicing process to separate individual semiconductor packages from one another.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2016
From: SHIH, SHING-YIH; WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 037962/0279 →