IP Library Granted Patent US 9,496,358
Granted Patent B2
US 9,496,358 · App. 14/289,936 · Granted Nov 15, 2016

Semiconductor device and fabrication method therefor

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,496,358
App. No.
14/289,936
Granted
Nov 15, 2016
Kind
B2
Abstract

A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Claims (20)

1. A fabrication method of a semiconductor electronic device structure having trench gate, comprising steps of:

providing a substrate having a trench disposed therein;

forming a gate dielectric layer on the surface in the trench;

partially filling the trench with electrode material for forming a gate electrode in the bottom of the trench, wherein the substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer;

carrying out a first angled implantation to dope impurities into the substrate through the side walls in the partially filled trench with the gate electrode disposed therein to form a first portion;

partially filling the trench with insulating material for forming an insulating cover layer disposed in the trench to cover the gate electrode;

carrying out a second angled implantation to dope impurities into the substrate through the side walls in the partially filled trench with both the gate electrode and the insulating cover layer disposed therein to form a second portion, wherein the dose of the second angled implantation is higher than the dose of the first angled implantation.

2. The fabrication method of a semiconductor electronic device structure of claim 1 ,

wherein the step of carrying out the first angled implantation comprises:

introducing an ion beam to the side walls of the trench at a first angle relative to the vertical direction of extension of the trench;

wherein the step of carrying out the second angled implantation comprises:

introducing an ion beam to the side walls of the trench at a second angle relative to the vertical direction of extension of the trench; and

wherein the first angle is smaller than the second angle.

3. The fabrication method of a semiconductor electronic device structure of claim 2 , wherein the first angle ranges from 5 to 15 degrees and the second angle ranges from 7 to 25 degrees.

4. The fabrication method of a semiconductor electronic device structure of claim 1 , further comprising the step of:

carrying out a blanket implantation to doping impurities into the substrate, wherein the dose of the blanket implantation is lighter than the dose of the second angled implantation.

5. The fabrication method of a semiconductor electronic device structure of claim 1 , further comprising the step of:

carrying out a blanket implantation to dope impurities into the substrate to form a third portion;

wherein the third portion is arranged atop the second portion;

wherein the first, the second and the third portions are connected with each other to form a triangular doped area.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2014
From: LEE, TZUNG-HAN; HU, YAW-WEN; SHIH, NENG-TAI; HSU, HENG HAO; CHANG, YU JING; CHIANG, HSU
To: INOTERA MEMORIES, INC.
Reel/Frame 033052/0773 →