Fan-out wafer level packaging and manufacturing method thereof
View Patent ↗A fan-out wafer-level-package (FOWLP) is provided. The FOWLP includes a redistribution layer (RDL) comprising a dielectric layer and a first metal layer; a passive device in the first metal layer; a first passivation layer covering a top surface of the RDL; a second passivation layer covering a bottom surface of the RDL; a chip mounted on the first passivation layer; a molding compound around the chip and on the first passivation layer; a via opening penetrating through the second passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a terminal of the chip; a contact opening in the second passivation layer; and a second metal layer in the via opening and the contact opening to electrically connect one electrode of the passive device with the terminal of the chip.
1. A fan-out wafer-level-package, comprising:
a redistribution layer (RDL) comprising at least one dielectric layer and at least one first metal layer;
a passive device in the first metal layer of the RDL;
a first passivation layer covering a top surface of the RDL;
a second passivation layer covering a bottom surface of the RDL;
at least one chip mounted on the first passivation layer, wherein the chip comprises a terminal distributed directly on an active surface of the chip in direct contact with the first passivation layer;
a molding compound disposed around the chip and on the first passivation layer;
a via opening penetrating through the first passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a portion of the terminal;
a contact opening in the second passivation layer, thereby exposing a portion of one electrode of the passive device; and
a second metal layer disposed on a lower surface of the second passivation layer wherein the via opening and the contact opening are filled with the second metal layer to electrically connect the electrode of the passive device with the terminal of the chip.
2. The fan-out wafer-level-package according to claim 1 , wherein the dielectric layer comprises inorganic material.
3. The fan-out wafer-level-package according to claim 2 , wherein the inorganic material comprises silicon nitride or silicon oxide.
4. The fan-out wafer-level-package according to claim 1 , wherein the passive device comprises a metal-insulator-metal (MIM) capacitor.
5. The fan-out wafer-level-package according to claim 1 , wherein the first passivation layer comprises benzocyclobutene (BCB).
6. The fan-out wafer-level-package according to claim 1 , wherein the first metal layer comprises aluminum, copper, tungsten, titanium, or titanium nitride.
7. The fan-out wafer-level-package according to claim 1 , wherein the second metal layer comprises copper.
8. The fan-out wafer-level-package according to claim 1 , wherein the second metal layer further comprises a solder pad on the second passivation layer.
9. The fan-out wafer-level-package according to claim 8 further comprising a solder ball on the solder pad.
10. The fan-out wafer-level-package according to claim 1 , wherein the terminal comprises a metal bump on an input/output (I/O) pad on the active surface of the chip.
11. The fan-out wafer-level-package according to claim 1 , wherein the RDL, the first passivation layer, and the second passivation layer function as an interposer.