Wafer level package and fabrication method thereof
View Patent ↗A semiconductor device includes a semiconductor device includes an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side; at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer; a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and a plurality of solder bumps mounted on the first passivation layer on the second side.
1. A semiconductor device, comprising:
an interposer having a first side and a second side opposite to the first side, wherein the interposer comprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on the first side and a second passivation layer on the second side;
at least one active chip mounted on the first passivation layer on the first side through a plurality of first bumps penetrating through the first passivation layer;
a molding compound disposed on the first side, the molding compound covering the at least one active chip and a top surface of the first passivation layer; and
a plurality of solder bumps mounted on the first passivation layer on the second side.
2. The semiconductor device according to claim 1 , wherein the first passivation layer comprises silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.
3. The semiconductor device according to claim 1 , wherein the second passivation layer comprises silicon nitride, silicon oxide, silicon oxynitride or a combination thereof.
4. The semiconductor device according to claim 1 , wherein the RDL further comprises a first interlayer dielectric between the first passivation layer and the second passivation layer, a first dielectric block layer between the first interlayer dielectric and the second passivation layer.
5. The semiconductor device according to claim 4 , wherein the first interlayer dielectric comprises silicon oxide, BSG, or BPSG.
6. The semiconductor device according to claim 4 , wherein the first dielectric block layer comprises silicon nitride.
7. The semiconductor device according to claim 4 , wherein a first metal layer is embedded in the first interlayer dielectric.
8. The semiconductor device according to claim 7 , wherein the RDL further comprises a second interlayer dielectric between the first passivation layer and first interlayer dielectric, a second dielectric block layer between the first interlayer dielectric and the second interlayer dielectric.
9. The semiconductor device according to claim 8 , wherein the second interlayer dielectric comprises silicon oxide, BSG, or BPSG.
10. The semiconductor device according to claim 8 , wherein the second dielectric block layer comprises silicon nitride.
11. The semiconductor device according to claim 8 , wherein the RDL further comprises a second metal layer and a first via in the second interlayer dielectric, wherein the second metal layer is electrically connected to the first metal layer through the first via.
12. The semiconductor device according to claim 8 , wherein the RDL further comprises a third dielectric block layer between the second interlayer dielectric and the first passivation layer.
13. The semiconductor device according to claim 12 , wherein the third dielectric block layer comprises silicon nitride.