IP Library Granted Patent US 10,008,461
Granted Patent B2
US 10,008,461 · App. 14/731,426 · Granted Jun 26, 2018

Semiconductor structure having a patterned surface structure and semiconductor chips including such structures

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Quick Facts
Patent No.
US 10,008,461
App. No.
14/731,426
Granted
Jun 26, 2018
Kind
B2
Abstract

A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

Claims (23)

1. A semiconductor structure, comprising:

a semiconductor substrate;

a metal layer over the semiconductor substrate;

a passivation layer over the metal layer, the passivation layer comprising at least one opening;

a patterned surface structure comprising portions of the passivation layer located in the at least one opening of the passivation layer and comprising a supporting portion; and

a conductive structure comprising a solder material located over the patterned surface structure and in direct contact with the metal layer through the at least one opening of the passivation layer, wherein portions of the conductive structure extend at least partially into the at least one opening of the passivation layer and contact substantially entire upper surfaces and sidewalls of the supporting portion of the patterned surface structure.

2. The semiconductor structure of claim 1 , wherein the conductive structure comprises a solder bump or a solder ball.

3. The semiconductor structure of claim 1 , wherein the supporting portion of the patterned surface structure comprises at least one of a mesh, regularly aligned pillars, or a concentric cylinder.

4. The semiconductor structure of claim 3 , wherein the supporting portion of the patterned surface structure comprises the regularly aligned pillars having a cross section comprising at least one of a polygon, a circle, or an oval.

5. The semiconductor structure of claim 1 , wherein the supporting portion of the patterned surface structure is made of at least one inorganic material such as silicon dioxide, silicon nitride, titanium dioxide, aluminum oxide, or at least one organic material such as polyimide, polybenzoxazole (PBO), or a combination thereof.

6. The semiconductor structure of claim 1 , wherein the conductive structure comprises at least one of Sn, Ag, Cu, Au, an alloy thereof or a combination thereof.

7. The semiconductor structure of claim 1 , wherein the opening of the passivation layer has a shape comprising at least one of a polygon, a circle, or an oval.

8. A semiconductor chip, comprising:

a substrate;

metal material over the substrate;

passivation material over the metal material, the passivation material comprising openings, at least some openings exposing a patterned surface structure comprising portions of the passivation material; and

conductive structures comprising a solder material located over the patterned surface structures, extending at least partially into the at least some openings of the passivation material, and in direct contact with the metal material, the conductive structure in contact with substantially entire upper surfaces and sidewalls of the patterned surface structure.

9. The semiconductor chip of claim 8 , wherein each of the passivation material and the patterned surface structures comprises a dielectric material comprising silicon dioxide, silicon nitride, titanium dioxide, or a combination thereof.

10. The semiconductor chip of claim 8 , wherein the patterned surface structures comprise at least one of a mesh, regularly aligned pillars, or at least one concentric cylinder.

11. The semiconductor chip of claim 10 , wherein the patterned surface structures comprise the regularly aligned pillars having a cross section comprising at least one of a polygon, a circle, or an oval.

12. The semiconductor chip of claim 10 , wherein the at least one concentric cylinder comprises two concentric cylinders.

13. The semiconductor chip of claim 8 , wherein the conductive structures comprise a solder bump or a solder ball.

14. The semiconductor chip of claim 8 , wherein the conductive structures comprise at least one of Sn, Ag, Cu, Au, an alloy thereof or a combination thereof.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2015
From: SHIH, SHING-YIH; WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 035798/0878 →