IP Library Granted Patent US 8,193,648
Granted Patent B2
US 8,193,648 · App. 12/758,289 · Granted Jun 5, 2012

Method for detecting errors of exposed positions of a pre-layer and a current layer by an integrated alignment and overlay mark

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Quick Facts
Patent No.
US 8,193,648
App. No.
12/758,289
Granted
Jun 5, 2012
Kind
B2
Abstract

An integrated alignment and overlay mark for detecting the exposed errors of the photolithography process between a pre-layer and a current layer is disclosed. The integrated alignment and overlay mark includes an alignment mark and an overlay mark in the same shot region. The alignment mark is formed surrounding the overlay mark; therefore, the gap or the orientation between the pre-layer and the current layer can be calculated in order to check the alignment accuracy of photolithography process.

Claims (17)

1. A method for detecting errors of exposed positions of a pre-layer and a current layer by an integrated alignment and overlay mark, the method comprising steps of:

forming an alignment mark of the integrated alignment and overlay mark on the pre-layer, and the alignment mark being formed in a shot region;

forming an overlay mark of the integrated alignment and overlay mark on the current layer, and the overlay mark being formed in the shot region and inside the alignment mark; and

making measurements of orientation and/or gap between the alignment mark and the overlay mark for detecting errors of exposed positions of the pre-layer and the current layer;

wherein the step of making measurements of orientation and/or gap between the alignment mark and the overlay mark further includes steps of:

making measurements of a first position on a first axis of the alignment mark, and a first position on a second axis of the alignment mark,

making measurements of a second position on the first axis of the overlay mark, and a second position on the second axis of the overlay mark; and

determining values of an error of the first position of the first axis and the second position of the first axis relative to a first predetermined error range, and determining values of an error of the first position of the second axis and the second position of the second axis relative to a second predetermined error range.

2. The method according to claim 1 , wherein in the step of forming an alignment mark of the integrated alignment and overlay mark on the pre-layer, a first alignment pattern and a second alignment pattern are formed, and the first and the second alignment patterns are constructed as a first frame.

3. The method according to claim 2 , wherein the first alignment pattern includes a plurality of first parallelly-linear alignment patterns, and the second alignment pattern includes a plurality of second parallelly-linear alignment patterns.

4. The method according to claim 3 , wherein in the step of forming an overlay mark of the integrated alignment and overlay mark on the current layer, the overlay mark includes a first overlay pattern and a second overlay pattern, and the first and the second overlay patterns are constructed as a second frame, and the second frame is disposed inside the first frame.

5. The method according to claim 4 , wherein the first overlay pattern includes a plurality of first parallelly-linear overlay patterns, the second overlay pattern includes a plurality of second parallelly-linear overlay patterns, the first parallelly-linear overlay patterns are parallel to the first parallelly-linear alignment patterns, and the second parallelly-linear overlay patterns are parallel to the second parallelly-linear alignment patterns.

6. The method according to claim 1 , wherein in the step of forming an alignment mark of the integrated alignment and overlay mark on the pre-layer, a first alignment pattern and a second alignment pattern are formed, and the first and the second alignment patterns are separated from each other.

7. The method according to claim 6 , wherein the first alignment pattern includes a plurality of first parallelly-linear alignment patterns, and the second alignment pattern includes a plurality of second parallelly-linear alignment patterns.

8. The method according to claim 7 , wherein in the step of forming an overlay mark of the integrated alignment and overlay mark on the current layer, the overlay mark includes a first overlay pattern and a second overlay pattern, and the first overlay pattern is disposed inside the first alignment pattern, and the second overlay pattern is disposed inside the second alignment pattern.

9. The method according to claim 8 , wherein the first overlay pattern includes a plurality of first parallelly-linear overlay patterns, the second overlay pattern includes a plurality of second parallelly-linear overlay patterns, the first parallelly-linear overlay patterns are parallel to the first parallelly-linear alignment patterns, and the second parallelly-linear overlay patterns are parallel to the second parallelly-linear alignment patterns.

10. The method according to claim 1 , further comprising a feedback step for providing a feedback signal to the exposure equipment a correction factor if the values of an error of the first position of the first axis and the second position of the first axis fall outside the first predetermined error range, and/or the values of an error of the first position of the second axis and the second position of the second axis fall outside the second predetermined error range after the step of determining values of the error.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2010
From: LAN, YUAN KU; LEE, CHUNG-YUAN
To: INOTERA MEMORIES, INC.
Reel/Frame 024221/0009 →