IP Library Patent Application 15003765
Patent Application
App. No. 15/003,765

SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF

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Quick Facts
Patent No.
US None
App. No.
15/003,765
Abstract

A semiconductor structure and a method of fabricating thereof are provided. The semiconductor structure includes a substrate and a capacitor structure. The substrate has a first blind hole and a trench. The first blind hole communicates with the trench. The first blind hole has a first depth, and the trench has a second depth smaller than the first depth. The capacitor structure includes a first inner conductor, a first inner insulator, and an outer conductor. The first inner conductor is in the first blind hole. The first inner insulator surrounds the first inner conductor. The outer conductor has a first portion surrounding the first inner insulator and an extending portion extending from the first portion. The first portion is in the first blind hole, and the extending portion is in the trench. The first inner conductor is separated from the outer conductor by the first inner insulator.

Claims (37)

1 . A semiconductor structure, comprising:

a substrate having a first blind hole and a trench, the first blind hole communicating with the trench, the first blind hole having a first depth, and the trench having a second depth smaller than the first depth; and

a capacitor structure, comprising:

a first inner conductor in the first blind hole;

a first inner insulator surrounding the first inner conductor; and

an outer conductor having a first portion surrounding the first inner insulator and an extending portion extending from the first portion, the first portion in the first blind hole, and the extending portion in the trench, wherein the first inner conductor is separated from the outer conductor by the first inner insulator.

2 . The semiconductor structure of claim 1 , wherein an area of the extending portion is smaller than a total area of the first portion, the first inner insulator and the first inner conductor in plan view.

3 . The semiconductor structure of claim 1 , wherein a thickness of the extending portion is smaller than a total thickness of the first portion, the first inner insulator and the first inner conductor.

4 . The semiconductor structure of claim 1 , further comprising:

a second blind hole communicating with the trench in the substrate;

a second portion of the outer conductor in the second blind hole;

a second inner insulator embedding in the second portion of the outer conductor; and

a second inner conductor embedding in the second inner insulator.

5 . The semiconductor structure of claim 4 , further comprising a first metal layer in contact with the outer conductor, and a second metal layer in contact with the first inner conductor and the second inner conductor.

6 . The semiconductor structure of claim 1 , further comprising an outer insulator between the substrate and the outer conductor.

7 . The semiconductor structure of claim 6 , wherein the outer insulator has a thickness smaller than the second depth of the trench.

8 . The semiconductor structure of claim 6 , wherein a combined thickness of the outer insulator and the extending portion is equal to the second depth of the trench.

9 . The semiconductor structure of claim 1 , wherein a thickness of the extending portion is equal to the second depth of the trench.

10 . The semiconductor structure of claim 1 , wherein a thickness of the extending portion is different from a thickness of the first portion.

11 . The semiconductor structure of claim 1 , wherein the capacitor structure is coplanar with the substrate.

12 . A method of fabricating a semiconductor structure, comprising:

forming a first blind hole and a trench in a substrate, the first blind hole communicating with the trench, the first blind hole having a first depth, and the trench having a second depth smaller than the first depth;

forming an outer conductor which has a first portion in the first blind hole and an extending portion in the trench;

forming a first inner insulator over the first portion; and

forming a first inner conductor over the first inner insulator and separated from the first portion by the first inner insulator.

13 . The method of claim 12 , further comprising:

forming a second blind hole communicating with the trench in the substrate;

forming a second portion of the outer conductor in the second blind hole;

forming a second inner insulator over the second portion; and

forming a second inner conductor over the second inner insulator and separated from the second portion by the second inner insulator.

14 . The method of claim 13 , wherein the second blind hole has a third depth larger than the second depth of the trench.

15 . The method of claim 13 , wherein the first depth of the first blind hole is different from the third depth of the second blind hole.

16 . The method of claim 12 , further comprising forming an outer insulator in the first blind hole and the trench, before forming the outer conductor.

17 . The method of claim 16 , wherein a thickness of the outer insulator is smaller than the second depth of the trench.

18 . The method of claim 12 , wherein the outer conductor fills the trench.

19 . The method of claim 12 , further comprising forming a first metal layer in contact with the outer conductor and a second metal layer in contact with the first inner conductor and the second inner conductor.

20 . The method of claim 12 , wherein forming the first blind hole and the trench is by laser drilling, dry etching, or wet etching.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2016
From: WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 037555/0221 →