IP Library Granted Patent US 9,397,048
Granted Patent B1
US 9,397,048 · App. 14/664,932 · Granted Jul 19, 2016

Semiconductor structure and manufacturing method thereof

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Quick Facts
Patent No.
US 9,397,048
App. No.
14/664,932
Granted
Jul 19, 2016
Kind
B1
Abstract

A semiconductor structure includes a substrate, a first through hole disposed in the substrate and filled with conductive material, and a second through hole disposed in the substrate and filled with isolation material, which a Young's modulus of the isolation material is smaller than a Young's modulus of the conductive material to balance stress from the conductive material.

Claims (17)

1. A semiconductor structure, comprising:

a substrate;

a first through hole disposed in the substrate and filled with conductive material; and

a second through hole disposed in the substrate and filled with isolation material, and a Young's modulus of the isolation material being smaller than a Young's modulus of the conductive material to balance stress from the conductive material.

2. The semiconductor structure of claim 1 , wherein the conductive material comprises copper, tungsten, polysilicon, or combination thereof.

3. The semiconductor structure of claim 1 , wherein the Young's modulus of the conductive material is over than 110 GPa.

4. The semiconductor structure of claim 1 , wherein the Young's modulus of the isolation material is smaller than 100 GPa.

5. The semiconductor structure of claim 4 , wherein the Young's modulus of the isolation material is in a range from about 5 GPa to about 100 GPa.

6. The semiconductor structure of claim 5 , wherein the Young's modulus of the isolation material is in a range from about 5 GPa to about 50 GPa.

7. The semiconductor structure of claim 1 , wherein the isolation material comprises spin-on glass, spin-on dielectric, polyimide, silicon dioxide, or combination thereof.

8. The semiconductor structure of claim 1 , wherein the second through hole is filled with isolation materials having different Young's modulus to form a multi-layer structure in the second through hole.

9. The semiconductor structure of claim 1 , wherein the first through hole and the second through comprise the same depth.

10. The semiconductor structure of claim 1 , wherein the first through hole and the second through comprise different depths.

11. The semiconductor structure of claim 1 , wherein the substrate comprises a first surface and a second surface opposite to the first surface.

12. The semiconductor structure of claim 11 , wherein the first through hole and the second through hole extend from the first surface to the second surface.

13. The semiconductor structure of claim 11 , wherein the first through hole and the second through hole extend from the second surface to the first surface.

14. The semiconductor structure of claim 1 , wherein the second through hole surrounds the first through hole.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 23, 2015
From: SHIH, SHING-YIH; WU, TIEH-CHIANG
To: INOTERA MEMORIES, INC.
Reel/Frame 035235/0595 →