Manufacturing method of capacitor structure and semiconductor device using the same
View Patent ↗The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.
1. A semiconductor device, comprising:
a semiconductor substrate;
at least one patterned reinforcing layer arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures;
a plurality of lower electrodes arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 2; and
a supporting layer arranged above the at least one patterned reinforcing layer and between the lower electrodes.
2. The semiconductor device according to claim 1 , wherein the semiconductor substrate includes a substrate, a plurality of buried bit lines, a plurality of bit line contacts, and a plurality of conductive structures, the buried bit lines are arranged in the substrate, the bit line contacts are arranged in the substrate at intervals of the buried bit lines, the conductive structures are arranged on the bit line contacts respectively for electrically connecting to the lower electrodes.
3. A semiconductor device, comprising:
a semiconductor substrate;
a first patterned reinforcing layer arranged above the semiconductor substrate, wherein the first patterned reinforcing layer has a plurality of first reinforcing structures configured to define a plurality of first alignment apertures;
a second patterned reinforcing layer arranged above the first patterned reinforcing, wherein the second patterned reinforcing layer has a plurality of second reinforcing structures configured to define a plurality of second alignment apertures;
a plurality of lower electrodes arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the first alignment apertures, being supported by the first reinforcing structures, and M of the lower electrodes pass through each of the second alignment apertures, being supported by the second reinforcing structures, where both N and M are integers greater than or equal to 2, and N is not equal to M; and
a supporting layer arranged above the second patterned reinforcing layer and between the lower electrodes.
4. The semiconductor device according to claim 3 , wherein the first alignment apertures are circular, triangle, rectangular, pentagon, or hexagon shaped, the second alignment apertures are circular, triangle, rectangular, pentagon, or hexagon shaped.
5. The semiconductor device according to claim 3 , wherein the semiconductor substrate includes a substrate, a plurality of buried bit lines, a plurality of bit line contacts, and a plurality of conductive structures, the buried bit lines are arranged in the substrate, the bit line contacts are arranged in the substrate at intervals of the buried bit lines, the conductive structures are arranged on the bit line contacts respectively for electrically connecting to the lower electrodes.