Memory structure having a floating body and method for fabricating the same
View Patent ↗A memory structure having a floating body is provided, which includes a substrate including an active area and an isolation structure surrounding the active area, a first source/drain region in the substrate in the active area, a first floating body in the substrate above the first source/drain region, a second floating body on the first floating body, a second source/drain region on the second floating body, and a trench-type gate structure in the substrate and beside the first floating body. A method of fabricating a memory structure having a floating body is also provided.
1. A memory structure, comprising:
a substrate comprising an active area and an isolation structure surrounding the active area;
a first source/drain region disposed in the substrate in the active area;
a first floating body disposed in the substrate above the first source/drain region, wherein the first floating body connects with the first source/drain region to have a first junction;
a second floating body disposed on the first floating body;
a second source/drain region disposed on the second floating body, wherein the second source/drain region connects with the second floating body to have a second junction; and
a trench-type gate structure disposed in the substrate and beside the first floating body.
2. The memory structure according to claim 1 , wherein,
a semiconductor material layer is disposed on the first floating body,
the second floating body is located at a lower portion of the semiconductor material layer, and
the second source/drain region is located at an upper portion of the semiconductor material layer and above the second floating body.
3. The memory structure according to claim 1 , wherein,
the trench-type gate structure comprises a gate and a gate dielectric layer disposed between the substrate and the gate, and
the memory structure further comprises a word line structure disposed above the gate and beside the second floating body.
4. The memory structure according to claim 3 , wherein a portion of the second source/drain region is directly above the word line structure.
5. The memory structure according to claim 1 , wherein,
the trench-type gate structure is disposed in a trench,
the trench-type gate structure comprises a gate and a gate dielectric layer disposed between the substrate and the gate, and
the memory structure further comprises a word line structure disposed above the gate and in the trench.
6. The memory structure according to claim 5 , wherein a portion of the second floating body is directly above the word line structure.
7. The memory structure according to claim 1 , wherein the trench-type gate structure comprises:
a gate, wherein the gate also serves as a word line;
a gate dielectric layer disposed between the substrate and the gate; and
a cap layer covering the gate.
8. The memory structure according to claim 7 , wherein a portion of the second floating body is directly above the trench-type gate structure.
9. The memory structure according to claim 1 , wherein the trench-type gate structure extends from the substrate to be above the substrate and beside the second floating body.
10. The memory structure according to claim 1 , further comprising a bit line disposed above the second source/drain region and electrically connecting to the second source/drain region.
11. The memory structure according to claim 1 , wherein one side of the trench-type gate structure abuts upon the isolation structure and a bottom of the trench-type gate structure is located within the first source/drain region.