Multi-device package and manufacturing method thereof
View Patent ↗A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.
1. A multi-device package, comprising:
at least two device regions formed from a substrate, and the substrate having a first surface and a second surface opposite to the first surface;
a first redistribution layer disposed on the first surface and electrically connected to the two device regions;
an external chip disposed on the first redistribution layer and at least electrically connected to the two device regions by the first redistribution layer;
a plurality of first connectors interposed between the first redistribution layer and the external chip to interconnect the two; and
a conductive contact extending from the second surface to the first surface of the substrate to electrically connect the device region.
2. The multi-device package of claim 1 , further comprising a plurality of second connectors below the second surface, and each of the second connectors being in contact with the conductive contact.
3. The multi-device package of claim 2 , wherein a diameter of the second connector is larger than a diameter of the first connector.
4. The multi-device package of claim 2 , wherein the first connectors and the second connectors are solder bumps or solder balls.
5. The multi-device package of claim 1 , further comprising a molding layer covering the external chip and the first redistribution layer.
6. The multi-device package of claim 1 , further comprising:
a second redistribution layer disposed below the second surface; and
a plurality of second connectors disposed below the second redistribution layer.
7. The multi-device package of claim 6 , wherein each of the first redistribution layer and the second redistribution layer comprises:
a plurality of metal layers arranged in parallel inside a dielectric layer; and
a plurality of vias, and the two adjacent metal layers being electrically connected by the via.
8. The multi-device package of claim 1 , wherein the device region comprises:
a semiconductor device;
an inter-layer dielectric layer covering the semiconductor device;
an inter-metal dielectric layer on the inter-layer dielectric layer; and
a metal interconnect structure through the inter-metal dielectric layer and the inter-layer dielectric layer, and an uppermost metal layer of the metal interconnect structure acting as a conductive pad of the device region.
9. The multi-device package of claim 8 , wherein the conductive contact is in contact with the conductive pad of the device region.
10. The multi-device package of claim 8 , wherein the semiconductor device is a memory device.
11. A multi-device package, comprising:
at least two device regions disposed in a substrate;
a first redistribution layer disposed on the substrate;
an external chip disposed on the first redistribution layer and at least electrically connected to the two device regions by the first redistribution layer;
a second redistribution layer disposed below the substrate; and
a conductive contact through the device region to interconnect the second redistribution layer and the device region.
12. A process of manufacturing a multi-device package, comprising:
providing a wafer having a first surface and a second surface opposite to the first surface, and the wafer having at least two device regions therein;
forming a first redistribution layer on the first surface, and the first redistribution layer being electrically connected to the two device regions;
forming a plurality of first connectors on the first redistribution layer;
mounting an external chip on the first connectors, and the external chip being at least electrically connected to the two device regions by the first redistribution layer and the first connectors; and
forming a conductive contact extending from the second surface to the first surface, and the conductive contact being electrically connected to the device regions.
13. The process of manufacturing the multi-device package of claim 12 , further comprising:
forming a molding layer covering the external chip;
forming a temporary adhesive layer on the molding layer;
thinning the wafer; and
removing the temporary adhesive layer.
14. The process of manufacturing the multi-device package of claim 13 , further comprising:
forming a plurality of second connectors below the second surface, and a diameter of the second connector being larger than a diameter of the first connector.
15. The process of manufacturing the multi-device package of claim 14 , further comprising:
dicing the wafer along a scribe line to form the multi-device package.
16. The process of manufacturing the multi-device package of claim 13 , further comprising:
forming a second redistribution layer below the second surface, and the second redistribution layer being electrically connected to the conductive contact; and
forming a plurality of second connectors below the second redistribution layer.
17. The process of manufacturing the multi-device package of claim 16 , further comprising:
dicing the wafer along a scribe line to form the multi-device package.
18. The process of manufacturing the multi-device package of claim 16 , wherein forming the second redistribution layer below the second surface comprises:
forming a dielectric material covering the second surface;
removing a portion of the dielectric material to form openings exposing the conductive contact;
forming vias in the openings;
forming a metal layer below the vias; and
patterning the metal layer.
19. The process of manufacturing the multi-device package of claim 12 , wherein forming the conductive contact extending from the second surface to the first surface comprises:
removing a portion of the wafer to form a through hole exposing a conductive pad of the device region; and
filling a conductive material in the through holes to form the conductive contact.
20. The process of manufacturing the multi-device package of claim 12 , wherein forming the first redistribution layer on the first surface comprises:
depositing a dielectric material covering the first surface;
removing a portion of the dielectric material to form openings exposing the device regions of the wafer;
forming vias in the openings;
forming a metal layer on the vias; and
patterning the metal layer.