Semiconductor memory device having enlarged cell contact area and method of fabricating the same
View Patent ↗A memory array includes a semiconductor substrate having thereon a plurality of active areas and trench isolation regions between the active areas. Buried word lines are disposed in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into three portions including a digit line contact area and two cell contact areas. Buried digit lines are disposed in the semiconductor substrate above the buried word lines. An epitaxial silicon layer extends from exposed sidewalls and a top surface of each of the cell contact areas.
1. A memory array, comprising:
a semiconductor substrate having thereon a plurality of active areas and a trench isolation region between the plurality of active areas, wherein each of the active areas extends along a first direction;
at least two buried word lines extending along a second direction in the semiconductor substrate, wherein the at least two of the buried word lines intersect with at least one of the active areas, the at least two of the buried word lines separating the at least one of the active areas into three portions including a digit line contact area and two cell contact areas, wherein the second direction is not perpendicular to the first direction, wherein each of the cell contact areas has exposed sidewalls and a top surface;
buried digit lines extending along a third direction in the semiconductor substrate above the buried word lines, wherein the third direction is substantially perpendicular to the second direction, wherein the buried digit lines have a top surface flush with the top surface of each of the cell contact areas; and
an epitaxial silicon layer extending from the exposed sidewalls and the top surface of each of the cell contact areas, wherein the epitaxial silicon layer has a top surface higher than the top surface of the buried digit lines.
2. The memory array according to claim 1 , wherein the buried digit lines intersect with the active areas at an acute angle θ.
3. The memory array according to claim 2 , wherein the acute angle θ ranges between 15°-60°.
4. The memory array according to claim 1 , further comprising a capacitor directly landing on the epitaxial silicon layer.
5. The memory array according to claim 1 , wherein each of the buried word lines comprises a conductive portion, a first cap layer situated atop the conductive portion, and an insulating layer between the conductive portion and the semiconductor substrate.
6. The memory array according to claim 5 , wherein the first cap layer extends along the second direction.
7. The memory array according to claim 6 , wherein each of the buried digit lines comprises a second cap layer extending along the third direction, and wherein the first cap layer intersects with the second cap layer.
8. The memory array according to claim 7 , wherein the epitaxial silicon layer is surrounded by the first cap layer and the second cap layer.
9. The memory array according to claim 1 , further comprising a recessed area between the digit line contact area and the epitaxial silicon layer.
10. The memory array according to claim 9 , wherein the recessed area is directly above the trench isolation region.