Method for fabricating a semiconductor device
A method of fabricating a semiconductor device. A wafer having a front side and a back side opposite to the front side is prepared. A plurality of through substrate vias (TSVs) is formed on the front side. A redistribution layer (RDL) is then formed on the TSVs. The wafer is bonded to a carrier. A wafer back side grinding process is performed to thin the wafer on the back side. An anneal process is performed to recrystallize the TSVs. A chemical-mechanical polishing (CMP) process is performed to polish the back side.
1. A method of fabricating a semiconductor device, comprising:
forming vias extending into a wafer from a front side thereof;
filling the vias with copper;
forming a redistribution layer (RDL) consisting of at least one dielectric layer and at least one metal layer comprising traces over the front side of the wafer, the traces connected to the copper filling the vias;
forming bumps on and connected to contact pads of the traces;
bonding a front side of the wafer to a carrier;
performing a grinding process to a back side of the wafer to thin the wafer on the back side to expose an end surface of the copper filling of each of the vias to form through substrate vias (TSVs);
after the end surface of the copper filling of each of the TSVs is exposed, performing an anneal process to recrystallize the copper filling the TSVs and form a copper extrusion on the end surface of the copper filling of each of the TSVs; and
performing a chemical-mechanical polishing (CMP) process to polish the back side of the wafer and remove the copper extrusions.
2. The method of fabricating a semiconductor device according to claim 1 , wherein forming the vias extending into the wafer from the front side thereof comprises:
forming holes from the front side of the wafer to a predetermined depth below the front side of the wafer; and
insulating interior surfaces of the holes with a dielectric layer before filling the holes with copper.
3. The method of claim 1 , further comprising performing another CMP process on the back side of the wafer after performing the grinding process and before performing the anneal process.
4. The method of claim 1 , wherein the anneal process is carried out at a temperature of about 200° C.
5. The method of claim 1 , further comprising de-bonding the carrier from the wafer after performing the CMP process.
6. The method of claim 1 , wherein forming vias extending into a wafer from a front side thereof comprises forming vias into a semiconductor wafer.
7. The method of claim 6 , further comprising selecting the semiconductor wafer to comprise silicon.
8. The method of claim 1 , wherein forming vias extending into a wafer from a front side thereof comprises forming vias into an in-process semiconductor structure.
9. The method of claim 1 , wherein forming a redistribution layer (RDL) consisting of at least one dielectric layer and at least one metal layer comprising traces over the front side of the wafer further comprises forming an RDL comprising multiple dielectric layers and at least one of multiple interconnection features and traces in the multiple dielectric layers.
10. The method of claim 1 , further comprising selecting the carrier to be a glass carrier or a silicon carrier.
11. The method of claim 1 , wherein forming vias extending into a wafer from a front side thereof comprises forming vias extending into a wafer of an initial thickness of between 700 μm and 800 μm.
12. The method of claim 1 , further comprising, after performing a chemical-mechanical polishing (CMP) process to polish the back side of the wafer and remove the copper extrusions, forming a passivation layer of the back side of the wafer.
13. The method of claim 1 , further comprising, after performing a chemical-mechanical polishing (CMP) process to polish the back side of the wafer and remove the copper extrusions, forming another redistribution layer (RDL) on the back side of the wafer.