IP Library Granted Patent US 9,437,583
Granted Patent B1
US 9,437,583 · App. 15/134,396 · Granted Sep 6, 2016

Package-on-package assembly and method for manufacturing the same

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Quick Facts
Patent No.
US 9,437,583
App. No.
15/134,396
Granted
Sep 6, 2016
Kind
B1
Abstract

A package-on-package (PoP) assembly includes a bottom die package and a top die package. The bottom die package includes an interposer having a first side and a second side, an active chip mounted on the first side within a chip mounting area through first bumps, and a dummy chip mounted on the first side within a peripheral area. The dummy chip is directly mounted on a passivation layer of the interposer. A dielectric layer covers the active chip and the dummy chip. At least one TSV connecter penetrates through the dielectric layer and the dummy chip. A molding compound is disposed on the first side. The molding compound covers the active chip and the TSV chip. Solder bumps are mounted on the second side.

Claims (13)

1. A package-on-package (PoP) assembly, comprising:

a bottom die package comprising

an interposer having a first side and a second side opposite to the first side;

at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps;

at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, wherein the dummy chip is directly mounted on a passivation layer of the interposer;

a dielectric layer covering the at least one active chip and the at least one dummy chip;

at least one TSV connecter penetrating through the dielectric layer and the dummy chip;

a molding compound disposed on the first side, the molding compound covering the at least one active chip and the at least one TSV chip; and

a plurality of solder bumps mounted on the second side;

a top die package mounted on the bottom die package.

2. The PoP assembly according to claim 1 , wherein the dummy chip is directly mounted on the passivation layer by using an adhesive.

3. The PoP assembly according to claim 1 , wherein TSV connecter is electrically connected to a metal trace pattern on the dielectric layer.

4. The PoP assembly according to claim 3 , wherein the top die package is mounted on the bottom die package through a plurality of second bumps disposed on the metal trace pattern.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2016
From: SHIH, SHING-YIH; SHIH, NENG-TAI
To: INOTERA MEMORIES, INC.
Reel/Frame 038337/0149 →