Low parasitic capacitance bit line process for stack DRAM
View Patent ↗A method of manufacturing low parasitic capacitance bit line for stack DRAM, comprising the following steps: offering a semi-conductor base, which semi-conductor having already included an oxide, plural word line stacks, plural bit line stacks and plural polysilicons; applying a multi layer resist coat; removing the multi layer resist coat and further removing parts of the oxide located on the polysilicon to form contact holes exposing the plural polysilicons; depositing an oxide layer; etching the oxide layer to form the oxide layer spacer; depositing a polysilicon layer; performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer that is column-shaped to form capacitor contacts; and using another oxide to fill into the space among the word line stacks and the capacitor contacts.
1. A method of manufacturing low parasitic capacitance bit line for stack dynamic random access memory (DRAM), comprising:
offering a semi-conductor base, which semi-conductor base having an oxide, plural word line stacks, plural bit line stacks and plural polysilicons, which oxide being placed on the plural word line stacks and on the plural polysilicons not stacked with the plural bit line stacks thereon;
applying a multi layer resist coat onto the upper surface of the semiconductor base;
removing the multi layer resist coat to form holes, and further removing the part of the oxide located over the plural polysilicons in the hole to form contact holes exposing the polysilicons;
depositing an oxide layer;
etching the oxide layer to form plural oxide layer spacers;
depositing a polysilicon layer;
performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer which is column-shaped to form capacitor contacts; and
using another oxide to fill into a space among the word line stacks and the capacitor contacts.
2. The method according to claim 1 , wherein the semiconductor base includes an array and a periphery.
3. The method according to claim 2 , wherein the plural word line stacks are adjacently placed in space with the plural polysilicons in the array, and the bit line stacks are stacked on parts of the plural polysilicons.
4. The method according to claim 2 , wherein the height of the multi layer resist coat is greater than those of the plural word line stacks.
5. The method according to claim 4 , wherein the multi layer resist coat is removed by means of lithography and etching.
6. The method according to claim 1 , wherein the etching performed to remove the oxide layer is anisotropic etching.
7. The method according to claim 1 , wherein the height of the polysilicon is greater than the one of the bit line stack.
8. The method according to claim 7 , wherein the part of the polysilicon which is higher than the bit line stack is removed by means of chemical machine polishing, and the upper surface of the polysilicon is planarized by grind polishing.
9. The method according to claim 1 , wherein the method used to fill the oxide into the space among the word line stacks and the capacitor contacts is Spin on Glass (SOG) method.
10. The method according to claim 1 , wherein the method used to fill the oxide into the space among the word line stacks and the capacitor contacts is Spin on Deposition (SOD) method.
11. The method according to claim 1 , wherein the method used to fill the oxide into the space among the word line stacks and the capacitor contacts is borophosphosilicate glass (BPSG) deposition.
12. A method of manufacturing low parasitic capacitance bit line for stack dynamic random access memory (DRAM), comprising:
offering a semi-conductor base, which semi-conductor base having an oxide and plural polysilicons, which oxide being placed on the plural polysilicons;
applying a multi layer resist coat onto the upper surface of the semiconductor base;
removing part of the multi layer resist coat, and further removing the part of the oxide located on the plural polysilicons to form contact holes exposing the polysilicons;
depositing an oxide layer;
etching the oxide layer to form plural oxide layer spacers;
depositing a polysilicon layer; and
performing lithography and etching on the polysilicon layer thereby allowing the rest of the polysilicon layer which is column-shaped to form capacitor contacts.
13. The method according to claim 12 , wherein in offering the semiconductor base, the semiconductor base further includes plural word line stacks and plural bit line stacks, and the oxide is placed on the plural word line stacks and on the plural bit line stacks not stacked with the plural word line stacks.
14. The method according to claim 13 , wherein the multi layer resist coat is removed by means of lithography and etching.
15. The method according to claim 13 , wherein the height of the polysilicon is greater than the one of the bit line stack.
16. The method according to claim 15 , wherein the part of the polysilicon which is higher than the bit line stack is removed by means of chemical machine polishing, and the upper surface of the polysilicon is planarized.
17. The method of manufacturing low parasitic capacitance bit line for stack DRAM according to claim 12 , wherein the etching performed to remove the oxide layer is anisotropic etching.
18. The method according to claim 12 , wherein after formation of the capacitor contact, another oxide is used to fill into a space among word line stacks and the capacitor contacts.