Semiconductor structure
View Patent ↗A semiconductor structure includes a semiconductor substrate, an active area in the semiconductor substrate, two trenches intersecting the active area to thereby divide the active area into a source region and two drain regions spaced apart from the source region, a saddle-shaped N+/N−/N+ structure in the source region of the active area; and two N+ drain doping regions in the two drain regions, respectively.
1. A semiconductor structure, comprising:
a semiconductor substrate;
an active area in the semiconductor substrate;
two trenches intersecting the active area to thereby divide the active area into a source region and two drain regions spaced apart from the source region;
a saddle-shaped N+/N−/N+ structure in the source region of the active area; and
two N+ drain doping regions in the two drain regions, respectively.
2. The semiconductor structure according to claim 1 further comprising two trench gates buried in lower portions of the two trenches respectively.
3. The semiconductor structure according to claim 2 wherein the saddle-shaped N+/N−/N+ structure comprises an N+ source doping region, two spaced apart N+ extension regions under the N+ source doping region, and an N− region under the N+ source doping region and sandwiched between the two N+ extension regions.
4. The semiconductor structure according to claim 3 wherein the two N+ extension regions partially overlap with the trench gates.
5. The semiconductor structure according to claim 3 wherein the two N+ extension regions extend downwardly along two sidewalls facing each other of the trenches, respectively.
6. The semiconductor structure according to claim 3 wherein the N+ source doping region and the two N+ drain doping regions have substantially a same junction depth.
7. The semiconductor structure according to claim 3 wherein the two N+ drain doping regions have a same junction depth that is shallower than that of the N+ source doping region.
8. The semiconductor structure according to claim 2 further comprising a dielectric layer filling upper portions of the two trenches.
9. The semiconductor structure according to claim 2 wherein two trench gates comprise a titanium nitride (TiN) layer and a tungsten (W) layer.
10. The semiconductor structure according to claim 1 further comprising a gate dielectric layer in the two trenches.