Wafer level package with TSV-less interposer
View Patent ↗A semiconductor device includes an interposer having a first side and a second side opposite to the first side; a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps; a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area; a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and a plurality of solder bumps mounted on the second side.
1. A semiconductor device, comprising:
an interposer having a first side and a second side opposite to the first side;
a first semiconductor die mounted on the first side within a first chip mounting area through a plurality of first bumps, wherein the first semiconductor die has a top surface and sidewall surfaces contiguous with the top surface;
a second semiconductor die mounted on the first side within a second chip mounting area being adjacent to the first chip mounting area;
a shielding feature directly disposed on the top surface and the sidewall surfaces of the first semiconductor die;
a ring-shaped supporting feature disposed on the first side and encompassing the first chip mounting area and the second chip mounting area; and
a plurality of solder bumps mounted on the second side, wherein no molding compound is disposed between the first semiconductor die and the second semiconductor die.
2. The semiconductor device according to claim 1 , wherein the interposer comprises a redistribution layer (RDL).
3. The semiconductor device according to claim 2 , wherein the RDL comprises at least one dielectric layer and at least one metal layer.
4. The semiconductor device according to claim 1 , wherein the interposer does not comprise a through silicon via (TSV) or a TSV substrate.
5. The semiconductor device according to claim 1 , wherein the first semiconductor comprises a graphics processing unit (GPU) or a central processing unit (CPU).
6. The semiconductor device according to claim 5 , wherein the second semiconductor comprises a memory chip.
7. The semiconductor device according to claim 1 , wherein the ring-shaped supporting feature is a 3D printed feature.
8. The semiconductor device according to claim 1 , wherein the shielding feature is disposed on the first semiconductor die.
9. The semiconductor device according to claim 1 , further comprising a packaging substrate connected to the plurality of solder bumps mounted on the second side of the interposer.
10. The semiconductor device according to claim 1 , wherein the ring-shaped supporting feature completely overlaps with a wafer dicing lane area.