Fabrication method for memory device
View Patent ↗The invention provides a method for fabricating a memory device. At first, a substrate having a plurality of gate electrode stacks and a source/drain region is provided, and a barrier layer and a sacrificial layer are sequentially formed on the substrate and cover the gate electrode stacks. A portion of the sacrificial layer is removed to form a sacrificial plug between the gate electrode stacks, and then a filling layer is formed over the substrate. Next, the sacrificial plug is removed, and a contact hole is formed. A clean step with a solution containing ammonia is carried out. The barrier layer at the bottom of the contact hole is removed, and a metal plug is then formed in the contact hole to electrically contact with the source/drain region.
1. A method for fabricating a memory device, comprising:
providing a substrate having a plurality of gate electrode stacks formed thereon and a doped region formed in the substrate between the gate electrode stacks;
depositing a barrier layer on the substrate and the gate electrode stacks;
forming a polysilicon sacrificial layer over the barrier layer;
removing a portion of the polysilicon sacrificial layer to form a polysilicon sacrificial plug between the gate electrode stacks;
forming a filling layer over the substrate between the gate electrode stacks;
removing the polysilicon sacrificial plug to form a contact hole;
performing a cleaning step with a solution containing ammonia for further removing the residue of the removed polysilicon sacrificial plug remained in the contact hole;
removing a portion of the barrier layer to expose the doped region; and
forming a metal plug in the contact hole to contact with the doped region.
2. The method as claimed in claim 1 , wherein the barrier layer is formed by a plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition or atomic layer deposition process.
3. The method as claimed in claim 1 , wherein the polysilicon sacrificial layer is formed by a plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition or atomic layer deposition process.
4. The method as claimed in claim 1 , wherein forming the polysilicon sacrificial plug comprises:
forming a hard mask layer on the polysilicon sacrificial layer; and
removing the portion of the polysilicon sacrificial layer;
removing the hard mask layer.
5. The method as claimed in claim 1 , wherein the polysilicon sacrificial layer is removed by an anisotropic etching process.
6. The method as claimed in claim 1 , wherein after the polysilicon sacrificial plug is removed, the method further comprises forming a diffusion barrier layer over the substrate.
7. The method as claimed in claim 1 , wherein the filling layer is formed by a low pressure chemical vapor deposition process.
8. The method as claimed in claim 1 , wherein after the filling layer is formed, the method further comprises performing a densification step.
9. The method as claimed in claim 1 , wherein after the filling layer is formed, the further comprises performing a planarization step.
10. The method as claimed in claim 9 , wherein the filling layer is flattened by a chemical mechanical polishing process.
11. The method as claimed in claim 1 , wherein the cleaning step with the solution containing ammonia is performed by a single wafer clean tool.