Granted Patent B2

US 9,257,553 · App. 14/504,385 · Granted Feb 9, 2016

Abstract

Claims (30)

1. A vertical transistor structure, comprising:

a substrate having a protruding structure;

an offset layer covering a top surface of the protruding structure; and

an interlayer on the offset layer, wherein the interlayer comprises a composite conductive layer formed from the offset layer and functions as a contact node of the vertical transistor structure, wherein the protruding structure is a cubic shaped structure.

2. The vertical transistor structure according to claim 1 wherein the substrate is a doped silicon substrate.

3. The vertical transistor structure according to claim 1 wherein the protruding structure is an island-like pillar.

4. The vertical transistor structure according to claim 1 wherein the offset layer is a deposited silicon layer.

5. The vertical transistor structure according to claim 1 further comprising a conductive layer atop the offset layer, wherein the conductive layer comprises tungsten or titanium.

6. The vertical transistor structure according to claim 5 wherein the composite conductive layer is a metal silicide between the offset layer and the conductive layer.

7. The vertical transistor structure according to claim 6 wherein the composite conductive layer comprises tungsten silicide.

8. The vertical transistor structure according to claim 1 wherein the interlayer comprises a conductive material layer.

9. The vertical transistor structure according to claim 8 wherein the conductive material layer comprises tungsten or titanium, wherein the composite conductive layer is a metal silicide between the offset layer and the conductive layer.

10. A method for fabricating a contact node of a vertical transistor structure, comprising:

providing a stack material layer comprising a hard mask layer, an offset layer, and a conductive layer;

patterning the hard mask layer to form an etch hard mask;

etching the stack material layer not covered by the etch hard mask to form a protruding structure; and

subjecting the stack material layer to an annealing process thereby forming an interlayer comprising a composite conductive layer, wherein the stack material layer comprises, in the order of, the hard mask layer, the conductive layer, and the offset layer, wherein the offset layer and the conductive layer react together to form the composite conductive layer.

11. The method according to claim 10 wherein the stack material layer further comprises a substrate and a conductive material layer, wherein the offset layer covers the substrate, and wherein the offset layer and the conductive layer react together to form the composite conductive layer.

12. The method according to claim 10 wherein the offset layer is a deposited silicon layer.

13. The method according to claim 10 wherein the conductive layer comprises tungsten or titanium.

14. The method according to claim 10 wherein the composite conductive layer is a metal silicide layer.

15. The method according to claim 10 wherein the interlayer further comprises a conductive material layer.

16. The method according to claim 10 wherein the conductive material layer comprises tungsten or titanium.

17. The method according to claim 10 further comprising:

performing an oxidation process to form a gate oxide layer on surfaces of the protruding structure.

18. The method according to claim 17 further comprising:

forming a spacer on surfaces of the protruding structure.

19. The method according to claim 18 further comprising:

forming a dielectric layer to cover the protruding structure; and

partially removing the dielectric layer, and removing the conductive layer without exposing underlying said interlayer.

Assignments (6)