Memory unit, memory unit array and method of manufacturing the same

1. A memory unit comprising:

a substrate having a surface;

at least one charge storage element;

at least one first recessed access element disposed in an active area of the substrate and extending from the surface into the substrate, wherein the first recessed access element is a recessed access transistor, the first recessed access element is electrically connected to the charge storage element and, the first recessed access element is for inducing in the substrate a first depletion region; and

an isolation portion adjacent to the active area and extending from the surface into the substrate, wherein the isolation portion includes a trenched isolating barrier and a second recessed access element, wherein the second recessed access element is disposed in the trenched isolating barrier for inducing in the substrate a second depletion region, and the trenched isolating barrier provides electrical insulation between the second recessed access element and the charge storage unit.

2. The memory unit according to claim 1 , wherein the charge storage element is a capacitor structure and the first recessed access element has a first recessed gate structure extending from the surface of the substrate into the substrate, the substrate in the active area has a first diffusion region and a second diffusion region respectively disposed at two sides of the first recessed gate structure, the first recessed access element is electrically connected to the charge storage element through the first diffusion region, and the trenched isolating barrier provides electrical insulation between the second recessed access element and the first diffusion region.

3. The memory unit according to claim 1 , wherein the second recessed access element has a second recessed gate structure disposed in a second gate recess in the trenched isolating barrier, and the second recessed gate structure includes a second dielectric layer disposed on the inner wall of the second gate recess and a second gate conductive layer disposed on the second gate dielectric layer.

4. The memory unit according to claim 1 , wherein the depth of the isolation portion is greater than the depth of the first recessed access element.

5. A memory unit array comprising:

a substrate having a plurality of active areas;

a plurality of first word lines and second word lines, wherein the first word lines correspondingly pass through the active areas, and the second word lines correspondingly pass through the intervals between the immediately adjacent active areas;

a plurality of bit lines;

a plurality of memory units formed in the substrate, and arranged into a plurality of rows and a plurality of columns, wherein the memory units are respectively disposed in the active areas of the substrate and each memory unit includes

at least one first recessed access element extending into the substrate for connecting one of the memory units to one of the corresponding first word line, wherein the first recessed access element has a recessed access transistor having a first recessed gate structure extending into the substrate and electrically connected to the corresponding first word line; and

at least one charge storage element electrically connected to the first recessed access element, wherein the charge storage element is electrically connected to one of the bit lines through the first recessed access element; and

a plurality of isolation portions extending into the substrate and correspondingly adjacent to the active areas, wherein each isolation portion includes a trenched isolating barrier and a second recessed access element, wherein the second recessed access element is disposed in the trenched isolating barrier, the trenched isolating barrier provides electrical insulation between the second recessed access element and the corresponding charge storage unit, and the second recessed access element is electrically connected to the corresponding second word line.

6. A method of manufacturing memory unit array comprising:

forming a plurality of memory units in a substrate, the memory units being respectively disposed in a plurality of active areas of the substrate, wherein each memory unit includes a first recessed access element and a charge storage element electrically connected to the first recessed access element, wherein the first recessed access element is a recessed access transistor having a first recessed gate structure extending into the substrate; and

forming a plurality of isolation portions in the substrate correspondingly adjacent to the memory units for isolating the memory units,

wherein each of the isolation portions extends into the substrate and each of the isolation portions includes a trenched isolating barrier and a second recessed access element, wherein the second recessed access element is disposed in the trenched isolating barrier, and the trenched isolating barrier provides electrical insulation between the second recessed access element and the charge storage element of the correspondingly memory unit.

7. The method of manufacturing memory unit array according to claim 6 , wherein in the step of forming the isolation portions includes: forming a shallow trenched isolation structure between the immediately adjacent active areas.

8. The method of manufacturing memory unit array according to claim 7 , wherein in the step of forming the isolation portions includes:

in each of the shallow trenched isolation structures,

etching the shallow trenched isolation structure to form a second gate recess in the shallow trenched isolation structure; and

forming a second recessed gate structure in the second gate recess, wherein the second recessed gate structure includes a second gate electric layer disposed on the inner wall of the second gate recess and a second gate conductive layer on the second gate dielectric layer.

9. The method of manufacturing memory unit array according to claim 8 , further comprising:

forming a plurality of first word lines and second word lines, wherein the first word lines correspondingly pass through the active areas, the second word lines correspondingly pass through the intervals between the immediately adjacent active areas, each of the first recessed gate structures is electrically connected to the corresponding first word line, and each of the second recessed gate structures is electrically connected to the corresponding second word line.

10. The method of manufacturing memory unit array according to claim 6 , wherein the depth of the isolation portion is greater than the depth of the first recessed access element.