Semiconductor devices comprising gate structure sidewalls having different angles
View Patent ↗The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.
1. A semiconductor device, comprising:
a substrate;
a first active region and a second active region disposed in the substrate, wherein the first active region is a source electrode, the second active region is a drain electrode, and a depth of the source electrode is greater than a depth of the drain electrode; and
a gate structure disposed in the substrate and between the first active region and the second active region, and the gate structure comprising:
a bottom;
a first sidewall attached to the first active region, the first sidewall and the bottom being linear and having a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate having a first included angle; and
a second sidewall attached to the second active region, the second sidewall being linear, the second sidewall and the bottom having a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate having a second included angle,
wherein the first included angle is less than the second included angle.
2. The semiconductor device of claim 1 , further comprising a gate dielectric layer disposed between the gate structure and the first active region and between the gate structure and the second active region.
3. The semiconductor device of claim 1 , wherein the gate structure comprises:
a first portion; and
a second portion disposed between the first portion and the first active region and between the first portion and the second active region.
4. The semiconductor device of claim 1 , wherein a memory cell comprises the first active region, the gate structure, and the second active region.
5. The semiconductor device of claim 4 , further comprising a plurality of isolation structures, and the memory cell disposed between two adjacent isolation structures.
6. A semiconductor device, comprising:
a substrate; and
a dual gate structure disposed in the substrate, the dual gate structure having two laterally adjacent gate stacks, and each of the two laterally adjacent gate stacks comprising:
a bottom;
a first sidewall, the first sidewall and the bottom being linear and having a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate having a first included angle, and the first sidewall of one gate stack of the two laterally adjacent gate stacks facing the first sidewall of another gate stack of the two laterally adjacent gate stacks; and
a second sidewall, the second sidewall being linear, the second sidewall and the bottom having a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate having a second included angle,
a first active region disposed in the substrate and between the two laterally adjacent gate stacks of the dual gate structure, wherein the first sidewall is attached to the first active region; and
a second active region disposed in the substrate, wherein each of the two laterally adjacent gate stacks is disposed between the first active region and the second active region, wherein the second sidewall is directly attached to the second active region,
wherein the first active region is a source electrode, the second active region is a drain electrode, a depth of the source electrode is greater than a depth of the drain electrode, and the first included angle is less than the second included angle.
7. The semiconductor device of claim 6 , wherein the first included angle is 0.5 to 10 degrees less than the second included angle.
8. The semiconductor device of claim 6 , further comprising a gate dielectric layer disposed between one of the gate stacks and the first active region and between one of the gate stacks and the second active region.
9. The semiconductor device of claim 6 , wherein each of the two laterally adjacent gate stacks of the dual gate structure comprises:
a first portion; and
a second portion disposed between the first portion and the first active region and between the first portion and the second active region.
10. The semiconductor device of claim 6 , wherein a memory cell is composed of the first active region, the dual gate structure, and two of the second active regions.
11. The semiconductor device of claim 10 , further comprising a plurality of isolation structures, and the memory cell disposed between adjacent two of the isolation structures.