IP Library Granted Patent US 8,236,464
Granted Patent B1
US 8,236,464 · App. 13/071,443 · Granted Aug 7, 2012

Method for fabricating a mask

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Quick Facts
Patent No.
US 8,236,464
App. No.
13/071,443
Granted
Aug 7, 2012
Kind
B1
Abstract

A method for making a mask, in which, an imprinting lithography process is employed to form a pattern in a first region of a mask substrate, and an E-beam writing process is employed to form another pattern in a second region of the mask substrate. Furthermore, these two patterns may be well stitched through an optical alignment process in an E-beam writing chamber.

Claims (36)

1. A method for fabricating a mask, comprising:

forming a master template comprising a first pattern;

providing a mask substrate comprising a light transparent substrate and a light-shielding material layer on the light transparent substrate, the mask substrate comprising a first region and a second region;

forming a first resist layer on the light-shielding material layer of the mask substrate;

imprinting the first resist layer in the first region with the master template to transfer the first pattern onto the first resist layer to form a second pattern;

etching the light-shielding material layer through the first resist layer to form a third pattern;

removing the first resist layer;

forming a second resist layer on the mask substrate;

performing an electron beam writing process on the second resist layer in the second region of the mask substrate using an electron beam, developing the second resist layer, and etching the mask substrate to form a fourth pattern onto the light-shielding material layer in the second region; and

removing the second resist layer.

2. The method according to claim 1 , wherein, after imprinting the first resist layer using the master template, the master template is removed from the first resist layer after the first resist layer is cured.

3. The method according to claim 1 , further comprising performing an alignment process, wherein, the electron beam writing process is carried out in a writing chamber, and the alignment process comprises:

providing a plurality of alignment marks on the mask substrate;

disposing a first light conductive element in the writing chamber and allowing the first light conductive element to extend to outside the writing chamber to connect with a light detecting device;

disposing a second light conductive element in the writing chamber and allowing the second light conductive element to extend to outside the writing chamber to connect with a light source;

allowing the light from the light source to be transmitted through the second light conductive element and incident on the mask substrate to produce a reflective light to be transmitted through the first light conductive element to the light detecting device, thereby to detect the alignment marks to orientate the mask substrate.

4. The method according to claim 3 , wherein the alignment marks are formed simultaneously with the formation of the third pattern using a process as same as the process for forming the third pattern.

5. A method for fabricating a mask, comprising:

forming a master template comprising a first pattern;

providing a mask substrate comprising a light transparent substrate and a light-shielding material layer on the light transparent substrate, the mask substrate comprising a memory cell array region and a peripheral logic region;

forming a first photo resist layer on the light-shielding material layer of the mask substrate;

imprinting the first photo resist layer in the memory cell array region with the master template to transfer the first pattern onto the first photo resist layer to form a second pattern;

etching the light-shielding material layer through the first photo resist layer to form a third pattern;

removing the first photo resist layer;

forming a second photo resist layer on the mask substrate;

performing an electron beam writing process on the second photo resist layer in the peripheral logic region of the mask substrate using an electron beam, developing the second photo resist layer, and etching the mask substrate to form a fourth pattern onto the light-shielding material layer in the peripheral logic region; and

removing the second photo resist layer.

6. The method according to claim 5 , further comprising performing an alignment process, wherein, the electron beam writing process is carried out in a writing chamber, and the alignment process comprises:

providing a plurality of alignment marks on the mask substrate;

disposing a first light conductive element in the writing chamber and allowing the first light conductive element to extend to outside the writing chamber to connect with a light detecting device;

disposing a second light conductive element in the writing chamber and allowing the second light conductive element to extend to outside the writing chamber to connect with a light source; and

allowing the light from the light source to be transmitted through the second light conductive element and incident on the mask substrate to produce a reflective light to be transmitted through the first light conductive element to the light detecting device, thereby to detect the alignment marks to orientate the mask substrate.

7. The method according to claim 6 , wherein the alignment marks are formed simultaneously with the formation of the third pattern using a process as same as the process for forming the third pattern.

8. The method according to claim 6 , wherein, each of the first light guide element and the second light guide element comprises an optical fiber.

9. The method according to claim 5 , wherein, after imprinting the first photo resist layer using the master template, the master template is removed from the first photo resist layer, and thereafter the first photo resist layer is cured.

10. The method according to claim 5 , wherein, after imprinting the first photo resist layer using the master template, the master template is removed from the first photo resist layer after the first photo resist layer is cured.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 24, 2011
From: SHIH, TAH-TE
To: INOTERA MEMORIES, INC.
Reel/Frame 026019/0106 →