Memory cell having a recessed gate and manufacturing method thereof
View Patent ↗A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.
1. A memory cell with a recessed gate, comprising:
a semiconductor substrate;
a shallow trench isolation, disposed in the semiconductor substrate so as to define an active region;
a source region, disposed on a side of the active region;
a drain region, disposed on another side of the active region, wherein a direction from the source region to the drain region is defined as a first direction;
a gate trench, disposed in the semiconductor substrate between the source region and the drain region, wherein the gate trench comprises a sidewall portion and a curved-bottom surface, and the curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction;
a gate electrode, disposed in the gate trench;
a halogen-doped dielectric layer, disposed between the gate electrode and the semiconductor substrate, wherein the halogen-doped dielectric layer is situated directly on the curved-bottom surface; and
at least a capacitor, electrically connected to the drain region.
2. The memory cell according to claim 1 , wherein the curved-bottom surface substantially has a three-dimensional saddle-shaped profile.
3. The memory cell according to claim 1 , wherein the sidewall portions comprise a first sidewall contiguous to the source region and a second sidewall contiguous to the drain region, and the first sidewall is opposite to the second sidewall along the first direction.
4. The memory cell according to claim 3 , wherein the halogen-doped dielectric layer is disposed on surfaces of the first sidewall, the second sidewall, and the curved-bottom surface.
5. The memory cell according to claim 3 , wherein the halogen-doped dielectric layer is disposed on a surface of the first sidewall.
6. The memory cell according to claim 3 , wherein the halogen-doped dielectric layer is disposed on an upper surface of the first sidewall.
7. The memory cell according to claim 1 , wherein the halogen-doped dielectric layer is a fluorine-containing dielectric layer and a concentration of fluorine atoms in the fluorine-containing dielectric layer substantially ranges from 1E11 atoms/cm 3 to 1E16 atoms/cm 3 .
8. The memory cell according to claim 1 , wherein the halogen-doped dielectric layer comprises halogen atoms.
9. The memory cell according to claim 1 , wherein the halogen-doped dielectric layer comprises silicon oxide, silicon oxynitride, or high-k dielectric.
10. The memory cell according to claim 1 , wherein the capacitor comprises stack capacitor or trench capacitor.
11. A method for fabricating a memory cell with a recessed gate, comprising:
providing a semiconductor substrate;
forming a shallow trench isolation in the semiconductor substrate so as to define an active region;
forming a source region on a side of the active region;
forming a drain region on another side of the active region, wherein a direction from the source region to the drain region is defined as a first direction;
forming a gate trench in the semiconductor substrate between the source region and the drain region, wherein the gate trench comprises a sidewall portion and a curved-bottom surface, and the curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction;
forming a gate dielectric layer in the gate trench;
after forming the gate dielectric layer, performing a halogen implantation process to implant halogen atoms into the gate dielectric layer thereby forming a halogen-doped dielectric layer on a surface of the gate trench;
filling a gate electrode into the gate trench, wherein the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate; and
forming at least a capacitor, wherein the capacitor electrically connects the drain region.
12. The method according to claim 11 , wherein the curved-bottom surface substantially has a three-dimensional saddle-shaped profile.
13. The method according to claim 11 , wherein the sidewall portions comprise a first sidewall contiguous to the source region and a second sidewall contiguous to the drain region, and the first sidewall is opposite to the second sidewall along the first direction.
14. The method according to claim 13 , wherein the halogen-doped dielectric layer is disposed on surfaces of the first sidewall, the second sidewall, and the curved-bottom surface.
15. The method according to claim 13 , wherein the halogen-doped dielectric layer is disposed on a surface of the first sidewall.
16. The method according to claim 13 , wherein the halogen-doped dielectric layer is disposed on an upper surface of the first sidewall.
17. The method according to claim 11 , wherein the halogen-doped dielectric layer is a fluorine-containing dielectric layer and a concentration of fluorine atoms in the fluorine-containing dielectric layer substantially ranges from 1E11 atoms/cm 3 to 1E16 atoms/cm 3 .
18. The method according to claim 11 , wherein the halogen-doped dielectric layer is formed prior to forming the drain region and the source region.
19. The method according to claim 11 , wherein the halogen implantation process comprises a fluorine ion implantation process.