IP Library Granted Patent US 8,283,709
Granted Patent B2
US 8,283,709 · App. 12/899,721 · Granted Oct 9, 2012

Semiconductor structure

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Quick Facts
Patent No.
US 8,283,709
App. No.
12/899,721
Granted
Oct 9, 2012
Kind
B2
Abstract

A semiconductor device is disclosed which includes a silicide substrate, a nitride layer, two STIs, and a strain nitride. The silicide substrate has two doping areas. The nitride layer is deposited on the silicide substrate. The silicide substrate and the nitride layer have a recess running through. The two doping areas are at two sides of the recess. The end of the recess has an etching space bigger than the recess. The top of the silicide substrate has a fin-shaped structure. The two STIs are at the two opposite sides of the silicide substrate (recess). The strain nitride is spacer-formed in the recess and attached to the side wall of the silicide substrate, nitride layer, two STIs. The two doping areas cover the strain nitride. As a result, the efficiency of semiconductor is improved, and the drive current is increased.

Claims (22)

1. A semiconductor structure comprising:

I. a silicide substrate having two doping areas;

II. a nitride layer disposed on the silicide substrate,

(a) the nitride layer and the silicide substrate having a recess structure formed thereon, the doping areas of the silicide substrate are respectively arranged on the opposite sides of the recess structure,

(b) the silicide substrate defines an etched space therein communicative with the lower end of the recess structure, the etched space having a cross section greater than that of the recess structure,

(c) a protruding structure exposingly formed in the etched space on the silicide substrate;

III. a pair of trench isolation areas disposed on the opposite sides of the silicide substrate and the recess (along the long symmetrical axis), wherein each trench isolation areas having a overlaying structure comprising an OX liner, a strain SiN liner, a SOD, and a HDP disposed from bottom to top in the above order; and

IV. a strained nitride coating disposed on the side wall that defines the recess structure covering the doping areas of the silicide substrate.

2. The semiconductor structure of claim 1 , wherein the strained nitride coating is a strained SiN liner.

3. The semiconductor structure of claim 1 , wherein the cross-section of the etching space is of a bottle shape.

4. The semiconductor structure of claim 1 , wherein the protruding structure is fin-shaped.

5. A semiconductor structure comprising:

I. a silicide substrate having a top surface and two doping areas formed thereon;

II. a nitride layer disposed on the top surface of silicide substrate, wherein

(a) a recess structure is formed into the nitride layer and the silicide substrate, the recess structure having a long symmetrical axis and a short symmetrical axis, wherein the doping areas of the silicide substrate are respectively arranged on the opposite sides of the recess structure above the bottom portion thereof and expose from the respective side walls of the recess structure,

(b) the silicide substrate defines an etched space therein at the bottom portion of the recess structure, the etched space having a cross section wider than that of the recess structure,

(c) a protruding structure is exposingly formed in the etched space on the silicide substrate at the bottom surface of the recess structure;

III. a pair of trench isolation areas disposed on the opposite sides of the silicide substrate and the recess along the long symmetrical axis, wherein each trench isolation areas having an overlying structure comprising an OX liner, a strain SiN liner, a SOD, and a HDP disposed from bottom to top in the above order; and

IV. a strained nitride coating selectively disposed on the side wall that defines the recess structure and covering the exposed portion of the doping area on the side wall of the recess structure above the bottom portion thereof.

6. The semiconductor structure of claim 1 , wherein the the strained nitride coating is a strained SiN liner.

7. The semiconductor structure of claim 1 , wherein the cross-section of the etching space is of a bottle shape.

8. The semiconductor structure of claim 1 , wherein the protruding structure is fin-shaped.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →