IP Library Granted Patent US 10,373,922
Granted Patent B2
US 10,373,922 · App. 14/731,382 · Granted Aug 6, 2019

Methods of manufacturing a multi-device package

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Quick Facts
Patent No.
US 10,373,922
App. No.
14/731,382
Granted
Aug 6, 2019
Kind
B2
Abstract

A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip and a plurality of first connectors. The two device regions are formed from the substrate, and the first redistribution layer is disposed on the substrate and electrically connected to the two device regions. The external chip is disposed on the first redistribution layer, and the first connectors are interposed between the first redistribution layer and the external chip to interconnect the two.

Claims (47)

1. A method of manufacturing a multi-device package, the method comprising:

forming at least two device regions from a wafer and within the wafer by using material of the wafer;

forming a first redistribution layer on the wafer, the first redistribution layer being electrically connected to the at least two device regions to electrically integrate the at least two device regions;

forming a plurality of first connectors on the first redistribution layer;

mounting an external chip on the plurality of first connectors, the external chip being electrically connected to the first redistribution layer by the plurality of first connectors;

forming a plurality of second connectors on the first redistribution layer, a diameter of a second connector of the plurality of second connectors being larger than a sum of a diameter of a first connector of the plurality of first connectors and a thickness of the external chip;

forming a temporary adhesive layer covering the plurality of second connectors and the external chip;

thinning the wafer;

removing the temporary adhesive layer; and

thereafter dicing the wafer along a scribe line to form the multi-device package.

2. The method of claim 1 , wherein mounting the external chip comprises mounting the external chip having a first through hole.

3. The method of claim 2 , further comprising:

forming a molding layer covering the first redistribution layer and the external chip;

removing a portion of the molding layer to form a second through hole and a third through hole, the second through hole exposing the first redistribution layer, the third through hole being through the first through hole to expose the first redistribution layer; and

filling a conductive material in the first through hole, the second through hole, and the third through hole to form a first conductive contact and a second conductive contact.

4. The method of claim 3 , further comprising:

forming a second redistribution layer on the molding layer, the second redistribution layer being electrically connected to the first conductive contact and the second conductive contact; and

forming a plurality of third connectors on the second redistribution layer.

5. The method of claim 4 , further comprising:

forming a temporary adhesive layer covering the plurality of third connectors and the second redistribution layer;

thinning the wafer; and

removing the temporary adhesive layer.

6. The method of claim 1 , wherein forming the first redistribution layer on the wafer comprises:

depositing a dielectric material covering the wafer;

removing a portion of the dielectric material to form openings exposing the at least two device regions of the wafer;

forming vias in the openings;

forming a metal layer on the vias; and

patterning the metal layer.

7. The method of claim 4 , wherein forming the second redistribution layer on the molding layer comprises:

forming a dielectric material covering the molding layer;

removing a portion of the dielectric material to form openings exposing the first conductive contact and the second conductive contact;

forming vias in the openings;

forming a metal layer on the vias; and

patterning the metal layer.

8. A method of manufacturing a multi-device package, the method comprising:

forming at least two device regions from a wafer and within the wafer by using material of the wafer;

forming a redistribution layer on the wafer, the redistribution layer being electrically connected to the at least two device regions to electrically integrate the at least two device regions;

forming a plurality of connectors on the redistribution layer;

mounting an external chip on the plurality of connectors, the external chip being electrically connected to the redistribution layer by the plurality of connectors;

performing testing of individual devices comprising the at least two device regions; and

thereafter dicing the wafer along a scribe line to form the multi-device package.

9. A method of manufacturing a multi-device package, the method comprising:

forming at least two device regions from a wafer and within the wafer by using material of the wafer;

forming a redistribution layer on the wafer, the redistribution layer being electrically connected to the at least two device regions to electrically integrate the at least two device regions, wherein forming the redistribution layer on the wafer comprises forming conductive pads recessed within the wafer, wherein the conductive pads form an uppermost metal layer of a metal interconnect structure of the first redistribution layer;

forming a plurality of connectors on the redistribution layer;

mounting an external chip on the plurality of connectors, the external chip being electrically connected to the redistribution layer by the plurality of connectors; and

thereafter dicing the wafer along a scribe line to form the multi-device package.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2015
From: KUAN, SHIH-FAN; LO, YI-JEN
To: INOTERA MEMORIES, INC.
Reel/Frame 035792/0034 →