Fabricating method of DRAM structure
View Patent ↗A fabricating method of a DRAM structure includes providing a substrate comprising a memory array region and a peripheral region. A buried gate transistor is disposed within the memory array region, and a planar gate transistor is disposed within the peripheral region. Furthermore, an interlayer dielectric layer covers the memory array region, the buried gate transistor and the planar gate transistor. Then, a capping layer of the planar gate transistor and part of the interlayer dielectric layer are removed simultaneously so that a first contact hole, a second contact hole and a third contact hole are formed in the interlayer dielectric layer. A drain doping region of the buried gate transistor is exposed through the first contact hole, a doping region of the planar gate transistor is exposed through the second contact hole, and a gate electrode of the planar gate transistor is exposed through the third contact hole.
1. A fabricating method of a dynamic random access memory (DRAM) structure, said DRAM structure being formed on a substrate comprising a memory array region and a peripheral region, at least one buried gate transistor disposed within said memory array region, at least one planar gate transistor disposed within said peripheral region, an interlayer dielectric layer covering said memory array region, said peripheral region, said buried gate transistor and said planar gate transistor, wherein said planar gate transistor comprises a planar gate electrode disposed on said substrate, a capping layer covers said planar gate electrode, a first source doping region and a first drain doping region are respectively disposed in said substrate adjacent to two sides of said planar gate electrode, said buried transistor comprises a buried gate electrode disposed in said substrate, and a second source doping region and a second drain doping region are respectively disposed in said substrate adjacent to two sides of said buried gate electrode, said fabricating method of the DRAM structure comprising:
removing part of said interlayer dielectric layer and said capping layer of said planar gate transistor to form a first contact hole, a second contact hole and a third contact hole in said interlayer dielectric layer, wherein said second drain doping region is exposed through said first contact hole, one of said first source doping region and said first drain doping region is exposed through said second contact hole and said planar gate electrode is exposed through said third contact hole;
forming a conductive layer to fill up said first contact hole, said second contact hole and said third contact hole and to cover said interlayer dielectric layer; and
patterning said conductive layer on said interlayer dielectric layer to form a first conductive pad, a second conductive pad and a third conductive pad on said interlayer dielectric layer so that said first conductive pad, said second conductive pad and said third conductive pad are respectively electrically connected to said conductive layer disposed within said first contact hole, within said second contact hole and within said third contact hole.
2. The fabricating method of the DRAM structure of claim 1 , further comprising:
forming a capacitor contacting said first conductive pad and electrically connected to said second drain doping region of said buried gate transistor after forming said first conductive pad, said second conductive pad and said third conductive pad.
3. The fabricating method of the DRAM structure of claim 1 , wherein a bit plug is disposed within said interlayer dielectric layer and contacting said second source doping region of said buried gate transistor.
4. The fabricating method of the DRAM structure of claim 1 , wherein said interlayer dielectric layer comprises silicon oxide.
5. The fabricating method of the DRAM structure of claim 1 , wherein said first contact hole, said second contact hole and said third contact hole are formed by means of a same reticle.