IP Library Granted Patent US 9,576,931
Granted Patent B1
US 9,576,931 · App. 15/047,632 · Granted Feb 21, 2017

Method for fabricating wafer level package

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Quick Facts
Patent No.
US 9,576,931
App. No.
15/047,632
Granted
Feb 21, 2017
Kind
B1
Abstract

A method for fabricating a wafer level package is disclosed. A carrier is provided. A redistributed layer (RDL) layer is formed on the carrier. Semiconductor dies are mounted on the RDL layer. The semiconductor dies are molded with a molding compound, thereby forming a molded wafer. A grinding process is then performed to remove a central portion of the molding compound, thereby forming a recess and an outer peripheral ring portion surrounding the recess. The carrier is then removed to expose a lower surface of the RDL layer. Solder bumps or solder balls are formed on the lower surface of the RDL layer.

Claims (18)

1. A method for fabricating a wafer level package, comprising:

providing a carrier;

forming a redistributed layer (RDL) layer on the carrier;

mounting semiconductor dies on the RDL layer;

molding the semiconductor dies with a molding compound, thereby forming a molded wafer;

subjecting the molded wafer to a grinding process to remove only a central portion of the molding compound from the molded wafer, thereby forming a recess in place of the removed central portion of the molding compound and an outer peripheral ring portion surrounding the recess, wherein the outer peripheral ring portion is thicker than the central portion;

removing the carrier to expose a lower surface of the RDL layer; and

forming solder bumps or solder balls on the lower surface of the RDL layer.

2. The method for fabricating a wafer level package according to claim 1 , wherein after removing the carrier, the method further comprises:

forming a solder mask on the lower surface of the RDL layer; and

forming openings in the solder mask to expose respective ball pads of the RDL layer.

3. The method for fabricating a wafer level package according to claim 2 , wherein the solder bumps or solder balls are formed on the respective ball pads.

4. The method for fabricating a wafer level package according to claim 1 , wherein after forming the solder bumps or solder balls, the method further comprises:

performing a cutting process to separating the outer peripheral ring portion from the molded wafer; and

performing a wafer dicing process to separate individual wafer level packages from one another.

5. The method for fabricating a wafer level package according to claim 1 , wherein before mounting the semiconductor dies on the RDL layer, the method further comprises:

forming a plurality of bumps on the RDL layer.

6. The method for fabricating a wafer level package according to claim 1 , wherein the RDL layer comprises at least one dielectric layer and at least one metal layer.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2016
From: SHIH, SHING-YIH
To: INOTERA MEMORIES, INC.
Reel/Frame 037771/0771 →