Semiconductor structure
View Patent ↗A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.
1. A semiconductor structure, comprising:
a substrate;
a first buried gate disposed in said substrate;
a second buried gate disposed in said substrate and adjacent to said first buried gate;
a first source disposed between said first buried gate and said second buried gate;
a first drain disposed at one side of said first buried gate;
a second source disposed at one side of said second buried gate;
an interlayer dielectric layer covering said first buried gate, said second buried gate and said substrate; and
a core dual damascene plug comprising a first plug, a second plug and an insulating slot, wherein said insulating slot is disposed between said first plug and said second plug and is recessed into a top surface of said interlayer dielectric layer so that said first plug and said second plug are mutually electrically insulated, and said first plug and said second plug respectively penetrate said interlayer dielectric layer to be respectively electrically connected to said first source and to said second source.
2. The semiconductor structure of claim 1 , wherein said core dual damascene plug is disposed right above said first source.
3. The semiconductor structure of claim 1 , wherein said core dual damascene plug is Π-shaped.
4. The semiconductor structure of claim 1 , wherein said insulating slot is disposed right above and between said first source and said second source.
5. The semiconductor structure of claim 1 , wherein the width of said insulating slot is smaller than that of said first buried gate.
6. The semiconductor structure of claim 1 , wherein the width of said insulating slot is smaller than that of said first plug and of said second plug.
7. The semiconductor structure of claim 1 , wherein said first plug and said second plug are respectively T-shaped to gain a maximized landing pad area.
8. The semiconductor structure of claim 1 , further comprising:
a bit line contact disposed in said interlayer dielectric layer and electrically connected to said first drain;
a bit line disposed in said interlayer dielectric layer, above said bit line contact and electrically connected to said bit line contact, wherein said bit line and said core dual damascene plug are mutually electrically insulated from each other; and
an insulating layer covering said bit line and directly contacting said insulating slot, wherein said first plug and said second plug respectively penetrate said insulating layer.
9. The semiconductor structure of claim 1 , further comprising:
a peripheral gate, disposed on said substrate and in said interlayer dielectric layer; and
a peripheral dual damascene plug integrally formed by said first plug and said second plug, wherein said peripheral dual damascene plug penetrate said interlayer dielectric layer to be electrically connected to said substrate as well as said peripheral gate, wherein said peripheral dual damascene plug is Π-shaped.
10. The semiconductor structure of claim 9 , wherein said peripheral dual damascene plug stays away from said core dual damascene plug and does not directly contact said bit line and said insulating layer at the same time.