IP Library Granted Patent US 8,604,620
Granted Patent B2
US 8,604,620 · App. 13/342,201 · Granted Dec 10, 2013

Semiconductor structure having lateral through silicon via

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Quick Facts
Patent No.
US 8,604,620
App. No.
13/342,201
Granted
Dec 10, 2013
Kind
B2
Abstract

The present invention provides a semiconductor structure having a lateral TSV and a manufacturing method thereof. The semiconductor structure includes a chip having an active side, a back side disposed opposite to the active side, and a lateral side disposed between the active side and the back side. The chip further includes a contact pad, a lateral TSV and a patterned conductive layer. The contact pad is disposed on the active side. The lateral TSV is disposed on the lateral side. The patterned conductive layer is disposed on the active side and is electrically connected to the lateral TSV and the contact pad.

Claims (13)

1. A semiconductor structure, comprising:

a chip having an active side, a back side opposite to said active side, and a lateral side between said active side and said back side, said chip further comprises:

a contact pad disposed on said active side of said chip;

a lateral TSV disposed on said lateral side; and

a patterned conductive layer disposed on said active side and electrically connected to said lateral TSV and said contact pad, wherein the lateral TSV and the patterned conductive layer are made from a same metal layer.

2. A semiconductor structure according to claim 1 , wherein said lateral side is at the outermost side of said chip.

3. A semiconductor structure according to claim 1 , wherein said TSV is provided with an exposed sidewall.

4. A semiconductor structure according to claim 3 , wherein said sidewall of said lateral TSV is leveled with said lateral side so that said TSV is embedded in said chip.

5. A semiconductor structure according to claim 1 , wherein said lateral TSV is substantially a semi-circular cylinder.

6. A semiconductor structure according to claim 1 , further comprising the chip according to claim 1 , wherein a chip is stacked over another chip so that the patterned conductive layer of the chip is electrically connected to the TSV of the another chip.

7. A semiconductor structure according to claim 1 , further comprising the chip according to claim 1 , wherein one chip is juxtaposed with another chip so that the lateral side of one of said chips is electrically connected with the lateral side of another chip.

8. A semiconductor structure according to claim 1 , further comprising a second chip stacked on the chip, wherein said second chip is provided with a second contact pad electrically connecting to said patterned conductive layer.

9. A semiconductor structure according to claim 1 , wherein said lateral TSV comprises metal.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050695/0825 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2017
From: INOTERA MEMORIES, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 041820/0815 →
SUPPLEMENT NO. 3 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041675/0105 →