Transistors and memory arrays

1. A transistor, comprising:

a semiconductor material panel between a first insulative material panel and a second insulative material panel; the first insulative material panel having a first trench extending downwardly therein and the second insulative material panel having a second trench extending downwardly therein;

the semiconductor material comprising a first post region and a second post region; the semiconductor material further comprising a fin region extending between the first and second post regions; each of the first and second post regions having a first thickness and the fin region having a second thickness, with the second thickness being less than the first thickness, the fin region comprising a lower part and an upper part that protrudes from the lower part, at least one of a pair of side surfaces of the fin region being substantially uneven at a connection portion between the lower part and the upper part;

gate dielectric material along sidewalls of the first and second post regions, along a top surface of the fin region, and along the side surfaces of the fin region;

gate material along the sidewalls of the first and second post regions, the top surface of the fin region and the side surfaces of the fin region;

a first source/drain region within the first post region; and

a second source/drain region within the second post region.

2. The transistor of claim 1 wherein the side surfaces of the fin region are along a first plane, and the sidewalls of the first and second post regions are along a second plane that intersects the first plane.

3. The transistor of claim 2 wherein the second plane is substantially orthogonal to the first plane.

4. The transistor of claim 1 wherein the second thickness is no more than about 40% of the first thickness.

5. A transistor, comprising:

a semiconductor material panel between a first insulative material panel and a second insulative material panel; the first insulative material panel having a first trench extending downwardly therein and the second insulative material panel having a second trench extending downwardly therein;

the semiconductor material comprising a first post region and a second post region; the semiconductor material further comprising a fin region extending between the first and second post regions; each of the first and second post regions having a first thickness and the fin region having a second thickness, with the second thickness being less than the first thickness, the fin region comprising a lower part and an upper part that protrudes from the lower part, at least one of a pair of side surfaces of the fin region being substantially uneven at a connection portion between the lower part and the upper part;

gate dielectric material along sidewalls of the first and second post regions, along a top surface of the fin region, and along the side surfaces of the fin region;

gate material along the sidewalls of the first and second post regions, the top surface of the fin region and the side surfaces of the fin region;

a first source/drain region within the first post region;

a second source/drain region within the second post region; and

wherein the first and second insulative material panels have downwardly-extending edges along sides of the first and second trenches, and wherein the first and second post regions are inset from the downwardly-extending edges of the first and second insulative material panels by a distance of at least about 2 nm.

6. The transistor of claim 5 wherein the second thickness is within a range of from about 2 nm to about 20 nm; and wherein the first thickness is within a range of from about 5 nm to about 50 nm.

7. A transistor, comprising:

a semiconductor material panel between a first insulative material panel and a second insulative material panel; the first insulative material panel having a first trench extending downwardly therein and the second insulative material panel having a second trench extending downwardly therein;

the semiconductor material comprising a first post region and a second post region; the semiconductor material further comprising a fin region extending between the first and second post regions; each of the first and second post regions having a first thickness and the fin region having a second thickness, with the second thickness being less than the first thickness, the fin region comprising a lower part and an upper part that protrudes from the lower part, at least one of a pair of side surfaces of the fin region being substantially uneven at a connection portion between the lower part and the upper part;

gate dielectric material along sidewalls of the first and second post regions, along a top surface of the fin region, and along the side surfaces of the fin region;

gate material along the sidewalls of the first and second post regions, the top surface of the fin region and the side surfaces of the fin region;

a first source/drain region within the first post region;

a second source/drain region within the second post region; and

wherein the first and second insulative material panels have downwardly-extending edges along sides of the first and second trenches, and wherein the first and second post regions are inset from the downwardly-extending edges of the first and second insulative material panels by a first inset distance that is along edges of the first and second post regions above the fin region, and wherein edges of the first and second post regions adjacent the fin region are inset from the downwardly-extending edges of the first and second insulative material panels by a second inset distance; the second inset distance being less than the first inset distance.