Programmable device, heirarchical parallel machines, and methods for providing state information
View Patent ↗Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.
1. A method of providing state information from a parallel machine to another device, wherein the parallel machine includes a plurality of programmable elements, wherein each of the programmable elements is configured to have a corresponding state, comprising:
determining state information, wherein the state information comprises the state of each of the programmable elements in the parallel machine;
compressing the state information, wherein compressing the state information comprises aggregating final states in a finite state machine implemented on the parallel machine; and
providing the compressed state information to the other device.
2. The method of claim 1 , wherein compressing the state information includes applying a lossless compression algorithm to the state information.
3. The method of claim 1 , wherein providing the compressed state information to the other device comprises providing the compressed state information to another parallel machine.
4. The method of claim 1 , wherein providing the compressed state information to the other device comprises providing the compressed state information to system memory.
5. A parallel machine comprising a plurality of programmable elements configured to implement at least one finite state machine, wherein the parallel machine is configured to:
determine state information, wherein the state information comprises the state of each of the programmable elements;
compress the state information, wherein the parallel machine being configured to compress the state information comprises the parallel machine being configured to aggregate final states of a finite state machine implemented on the parallel machine; and
provide the compressed state information to another device.
6. The parallel machine of claim 5 , wherein the other device comprises a second parallel machine, wherein the second parallel machine is configured to receive and process the compressed state information.
7. The parallel machine of claim 5 , further comprising Boolean logic configured to aggregate the final states.
8. A parallel machine comprising:
a plurality of programmable elements configured to implement one or more finite state machines, wherein the plurality of programmable elements are configured to receive a N-digit input and provide a M-digit output as a function of the N-digit input, wherein the M-digit output is formed by compressing state information from each of the programmable elements, wherein the plurality of programmable elements is configured to send the M-digit output to another plurality of programmable elements; and
logic configured to aggregate output from two or more of the programmable elements used to implement a same one of the finite state machines.
9. The parallel machine of claim 8 , wherein N equals M.
10. The parallel machine of claim 8 , wherein M is an integer multiple of N.
11. The parallel machine of claim 8 , wherein the programmable elements are configured to implement a logical group of N state machines, wherein the outputs of the N state machines are aggregated to provide the M-digit output.
12. The parallel machine of claim 8 , wherein the plurality of programmable elements comprises one of two or more groups of programmable elements.
13. The parallel machine of claim 12 , further comprising:
a N-digit input interface coupled to the one group of programmable elements and configured to receive the N-digit input; and
a M-digit output interface coupled to the one group of programmable elements and configured to provide the M-digit output.
14. The parallel machine of claim 12 , wherein the one group of programmable elements comprises a block of programmable elements.
15. The parallel machine of claim 14 , wherein the block of programmable elements comprises a plurality of rows of programmable elements, wherein each of the rows is coupled to a respective one of a plurality of intra-block switches.
16. The parallel machine of claim 15 , wherein the programmable elements in each of the rows comprises:
a plurality of groups of two state machine elements; and
another programmable element.
17. The parallel machine of claim 12 , further comprising:
a programmable switch configured to selectively couple the one group of programmable elements to another one of the groups of programmable elements, an input port, and/or an output port.
18. The parallel machine of claim 17 , further comprising:
a register configured to store a program configured to program the plurality of programmable elements and the plurality of programmable switches.